From: Geert Uytterhoeven <geert@linux-m68k.org> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cc: Rob Herring <robh+dt@kernel.org>, Magnus Damm <magnus.damm@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>, Linux ARM <linux-arm-kernel@lists.infradead.org>, Biju Das <biju.das.jz@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Chris Brandt <Chris.Brandt@renesas.com> Subject: Re: [PATCH 10/16] serial: sh-sci: Add support for RZ/G2L SoC Date: Fri, 21 May 2021 15:26:45 +0200 [thread overview] Message-ID: <CAMuHMdXNzvTW920fJ2fKDWe=+CppfRdThKudTh51EW4fY2eRFg@mail.gmail.com> (raw) In-Reply-To: <20210514192218.13022-11-prabhakar.mahadev-lad.rj@bp.renesas.com> Hi Prabhakar, On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Biju Das <biju.das.jz@bp.renesas.com> > > Add serial support for RZ/G2L SoC with earlycon and > extended mode register support. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/drivers/tty/serial/sh-sci.c > +++ b/drivers/tty/serial/sh-sci.c > @@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { > [SCFDR] = { 0x0E, 16 }, > [SCSPTR] = { 0x10, 16 }, > [SCLSR] = { 0x12, 16 }, > + [SEMR] = { 0x14, 8 }, This is the parameter section for RZ/T and RZ/A2. Please update the comments above, to say this also applies to RZ/G2L. I can confirm the documentation for RZ/T1 and RZ/A2 agrees about the existence and behavior of SEMR. > }, > .fifosize = 16, > .overrun_reg = SCLSR, > @@ -2527,6 +2528,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, > case 27: smr_val |= SCSMR_SRC_27; break; > } > smr_val |= cks; > + if (sci_getreg(port, SEMR)->size) > + serial_port_out(port, SEMR, 0); As this is done in both branches of the if() statement, I think it should be moved up. > serial_port_out(port, SCSCR, scr_val | s->hscif_tot); > serial_port_out(port, SCSMR, smr_val); > serial_port_out(port, SCBRR, brr); > @@ -2561,6 +2564,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, > scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); > smr_val |= serial_port_in(port, SCSMR) & > (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); > + if (sci_getreg(port, SEMR)->size) > + serial_port_out(port, SEMR, 0); (else branch) > serial_port_out(port, SCSCR, scr_val | s->hscif_tot); > serial_port_out(port, SCSMR, smr_val); > } > @@ -3170,6 +3175,10 @@ static const struct of_device_id of_sci_match[] = { > .compatible = "renesas,scif-r7s9210", > .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), > }, > + { > + .compatible = "renesas,scif-r9a07g044", > + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), > + }, > /* Family-specific types */ > { > .compatible = "renesas,rcar-gen1-scif", The rest looks good to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
WARNING: multiple messages have this Message-ID
From: Geert Uytterhoeven <geert@linux-m68k.org> To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Cc: Rob Herring <robh+dt@kernel.org>, Magnus Damm <magnus.damm@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Jiri Slaby <jirislaby@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, "open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>, Linux ARM <linux-arm-kernel@lists.infradead.org>, Biju Das <biju.das.jz@bp.renesas.com>, Prabhakar <prabhakar.csengg@gmail.com>, Chris Brandt <Chris.Brandt@renesas.com> Subject: Re: [PATCH 10/16] serial: sh-sci: Add support for RZ/G2L SoC Date: Fri, 21 May 2021 15:26:45 +0200 [thread overview] Message-ID: <CAMuHMdXNzvTW920fJ2fKDWe=+CppfRdThKudTh51EW4fY2eRFg@mail.gmail.com> (raw) In-Reply-To: <20210514192218.13022-11-prabhakar.mahadev-lad.rj@bp.renesas.com> Hi Prabhakar, On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Biju Das <biju.das.jz@bp.renesas.com> > > Add serial support for RZ/G2L SoC with earlycon and > extended mode register support. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/drivers/tty/serial/sh-sci.c > +++ b/drivers/tty/serial/sh-sci.c > @@ -306,6 +306,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { > [SCFDR] = { 0x0E, 16 }, > [SCSPTR] = { 0x10, 16 }, > [SCLSR] = { 0x12, 16 }, > + [SEMR] = { 0x14, 8 }, This is the parameter section for RZ/T and RZ/A2. Please update the comments above, to say this also applies to RZ/G2L. I can confirm the documentation for RZ/T1 and RZ/A2 agrees about the existence and behavior of SEMR. > }, > .fifosize = 16, > .overrun_reg = SCLSR, > @@ -2527,6 +2528,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, > case 27: smr_val |= SCSMR_SRC_27; break; > } > smr_val |= cks; > + if (sci_getreg(port, SEMR)->size) > + serial_port_out(port, SEMR, 0); As this is done in both branches of the if() statement, I think it should be moved up. > serial_port_out(port, SCSCR, scr_val | s->hscif_tot); > serial_port_out(port, SCSMR, smr_val); > serial_port_out(port, SCBRR, brr); > @@ -2561,6 +2564,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, > scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); > smr_val |= serial_port_in(port, SCSMR) & > (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); > + if (sci_getreg(port, SEMR)->size) > + serial_port_out(port, SEMR, 0); (else branch) > serial_port_out(port, SCSCR, scr_val | s->hscif_tot); > serial_port_out(port, SCSMR, smr_val); > } > @@ -3170,6 +3175,10 @@ static const struct of_device_id of_sci_match[] = { > .compatible = "renesas,scif-r7s9210", > .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), > }, > + { > + .compatible = "renesas,scif-r9a07g044", > + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), > + }, > /* Family-specific types */ > { > .compatible = "renesas,rcar-gen1-scif", The rest looks good to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-21 13:27 UTC|newest] Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-14 19:22 [PATCH 00/16] Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 01/16] dt-bindings: arm: renesas: Document Renesas RZ/G2UL SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-18 1:31 ` Rob Herring 2021-05-18 1:31 ` Rob Herring 2021-05-21 13:22 ` Geert Uytterhoeven 2021-05-21 13:22 ` Geert Uytterhoeven 2021-05-21 16:54 ` Lad, Prabhakar 2021-05-21 16:54 ` Lad, Prabhakar 2021-05-27 11:29 ` Geert Uytterhoeven 2021-05-27 11:29 ` Geert Uytterhoeven 2021-05-27 11:47 ` Lad, Prabhakar 2021-05-27 11:47 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} SoC variants Lad Prabhakar 2021-05-14 19:22 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L, LC} " Lad Prabhakar 2021-05-18 1:31 ` Rob Herring 2021-05-18 1:31 ` Rob Herring 2021-05-21 13:23 ` [PATCH 02/16] dt-bindings: arm: renesas: Document Renesas RZ/G2{L,LC} " Geert Uytterhoeven 2021-05-21 13:23 ` Geert Uytterhoeven 2021-05-21 17:09 ` Lad, Prabhakar 2021-05-21 17:09 ` Lad, Prabhakar 2021-05-27 11:28 ` Geert Uytterhoeven 2021-05-27 11:28 ` Geert Uytterhoeven 2021-05-27 11:49 ` Lad, Prabhakar 2021-05-27 11:49 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 03/16] dt-bindings: arm: renesas: Document SMARC EVK Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-18 1:32 ` Rob Herring 2021-05-18 1:32 ` Rob Herring 2021-05-21 13:24 ` Geert Uytterhoeven 2021-05-21 13:24 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} for the new RZ/G2{L, LC} SoC's Lad Prabhakar 2021-05-21 13:25 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} for the new RZ/G2{L,LC} SoC's Geert Uytterhoeven 2021-05-21 13:25 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Geert Uytterhoeven 2021-05-21 17:21 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} " Lad, Prabhakar 2021-05-21 17:21 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Lad, Prabhakar 2021-05-27 11:47 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L,LC} " Geert Uytterhoeven 2021-05-27 11:47 ` [PATCH 04/16] soc: renesas: Add ARCH_R9A07G044{L, LC} " Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 05/16] arm64: defconfig: Enable ARCH_R9A07G044{L,LC} Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} Lad Prabhakar 2021-05-14 19:22 ` [PATCH 06/16] dt-bindings: arm: renesas, prr: Add new compatible string for RZ/G{L, LC, UL} Lad Prabhakar 2021-05-18 1:33 ` Rob Herring 2021-05-18 1:33 ` Rob Herring 2021-05-21 13:25 ` [PATCH 06/16] dt-bindings: arm: renesas,prr: Add new compatible string for RZ/G{L,LC,UL} Geert Uytterhoeven 2021-05-21 13:25 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 07/16] soc: renesas: Add support to read LSI DEVID register Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 08/16] soc: renesas: Add support to identify RZ/G2{L,LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 08/16] soc: renesas: Add support to identify RZ/G2{L, LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 09/16] dt-bindings: serial: renesas,scif: Document r9a07g044 bindings Lad Prabhakar 2021-05-14 19:22 ` [PATCH 09/16] dt-bindings: serial: renesas, scif: " Lad Prabhakar 2021-05-18 1:33 ` Rob Herring 2021-05-18 1:33 ` Rob Herring 2021-05-21 13:26 ` [PATCH 09/16] dt-bindings: serial: renesas,scif: " Geert Uytterhoeven 2021-05-21 13:26 ` Geert Uytterhoeven 2021-05-21 15:15 ` Geert Uytterhoeven 2021-05-21 15:15 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 10/16] serial: sh-sci: Add support for RZ/G2L SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 13:26 ` Geert Uytterhoeven [this message] 2021-05-21 13:26 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-18 1:35 ` Rob Herring 2021-05-18 1:35 ` Rob Herring 2021-05-21 15:04 ` Geert Uytterhoeven 2021-05-21 15:04 ` Geert Uytterhoeven 2021-05-21 18:42 ` Lad, Prabhakar 2021-05-21 18:42 ` Lad, Prabhakar 2021-05-27 11:51 ` Geert Uytterhoeven 2021-05-27 11:51 ` Geert Uytterhoeven 2021-05-14 19:22 ` [PATCH 12/16] clk: renesas: Define RZ/G2L CPG Clock Definitions Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 15:03 ` Geert Uytterhoeven 2021-05-21 15:03 ` Geert Uytterhoeven 2021-05-21 15:19 ` Geert Uytterhoeven 2021-05-21 15:19 ` Geert Uytterhoeven 2021-05-21 18:37 ` Lad, Prabhakar 2021-05-21 18:37 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 13/16] clk: renesas: Add CPG core wrapper for RZ/G2L SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 15:02 ` Geert Uytterhoeven 2021-05-21 15:02 ` Geert Uytterhoeven 2021-05-27 12:04 ` Geert Uytterhoeven 2021-05-27 12:04 ` Geert Uytterhoeven 2021-05-28 7:51 ` Lad, Prabhakar 2021-05-28 7:51 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 14/16] clk: renesas: Add support for R9A07G044L SoC Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-14 19:22 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Lad Prabhakar 2021-05-14 19:22 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L, LC} SoC's Lad Prabhakar 2021-05-21 15:35 ` [PATCH 15/16] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's Geert Uytterhoeven 2021-05-21 15:35 ` Geert Uytterhoeven 2021-05-21 18:36 ` Lad, Prabhakar 2021-05-21 18:36 ` Lad, Prabhakar 2021-05-27 11:17 ` Geert Uytterhoeven 2021-05-27 11:17 ` Geert Uytterhoeven 2021-05-27 11:51 ` Lad, Prabhakar 2021-05-27 11:51 ` Lad, Prabhakar 2021-05-14 19:22 ` [PATCH 16/16] arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK Lad Prabhakar 2021-05-14 19:22 ` Lad Prabhakar 2021-05-21 15:40 ` Geert Uytterhoeven 2021-05-21 15:40 ` Geert Uytterhoeven 2021-05-21 18:21 ` Lad, Prabhakar 2021-05-21 18:21 ` Lad, Prabhakar
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