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[209.85.221.180]) by smtp.gmail.com with ESMTPSA id 29sm22627vkl.6.2021.12.17.02.55.29 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Dec 2021 02:55:29 -0800 (PST) Received: by mail-vk1-f180.google.com with SMTP id m185so1246462vkm.5 for ; Fri, 17 Dec 2021 02:55:29 -0800 (PST) X-Received: by 2002:a05:6122:104f:: with SMTP id z15mr855694vkn.39.1639738529014; Fri, 17 Dec 2021 02:55:29 -0800 (PST) MIME-Version: 1.0 References: <20211217090248.259122-1-miquel.raynal@bootlin.com> <20211217090248.259122-3-miquel.raynal@bootlin.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 17 Dec 2021 11:55:17 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 2/4] mtd: rawnand: rzn1: Add new NAND controller driver To: Wolfram Sang Cc: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , MTD Maling List , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Milan Stevanovic , Jimmy Lalande , Thomas Petazzoni , Linux-Renesas , Magnus Damm , Gareth Williams , Phil Edworthy , Ralph Siemsen , Chris Brandt , Miquel Raynal X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_025532_026447_457544C4 X-CRM114-Status: GOOD ( 25.00 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Hi Wolfram, CC Chris Brandt On Fri, Dec 17, 2021 at 11:16 AM Wolfram Sang wrote: > On Fri, Dec 17, 2021 at 10:02:46AM +0100, Miquel Raynal wrote: > > Introduce Renesas RZ/N1x NAND controller driver which supports: > > - All ONFI timing modes > > - Different configurations of its internal ECC controller > > - On-die (not tested) and software ECC support > > - Several chips (not tested) > > - Subpage accesses > > - DMA and PIO > > > > This controller was originally provided by Evatronix before being bought > > by Cadence. > > > > Signed-off-by: Miquel Raynal > > Tested-by: Ralph Siemsen > > This IP core is also available on some Renesas R-Car Gen3 SoCs. I don't > have a board with NAND equipped, so I sadly cannot test your patch and > can only say that the code looks like it is in a really good shape and > can only suggest some renaming. Also on RZ/A2M. RZ/A1 seems to use a different one. Note that RZ/N1 NANDC claims to support up to ONFI2.2, while R-Car Gen3 and RZ/A2M do ONFI1.x only? Chris: usually you are good at IP history ;-) Do you have anything to add? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D835C433FE for ; Fri, 17 Dec 2021 11:02:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232193AbhLQLC2 (ORCPT ); Fri, 17 Dec 2021 06:02:28 -0500 Received: from mail-pf1-f178.google.com ([209.85.210.178]:33564 "EHLO mail-pf1-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232148AbhLQLC1 (ORCPT ); Fri, 17 Dec 2021 06:02:27 -0500 Received: by mail-pf1-f178.google.com with SMTP id x5so2004501pfr.0; Fri, 17 Dec 2021 03:02:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CzRODjcJJkmc7LYh+2mnvUIKs4AKBEWasXQMzh6C4sI=; b=WoCwcNccYAZOS1duN0R4QjMvx1jQb5RHN/AAd9VcRYpHRKg9/jhjArRT7Y0/jz0uqn 0yXvyGwaSPPxyfA9ZNVqMsVyqD3aRKwdHgWxSTNSC0sZ//ZKijIe/jWGnxkgnzcU+mnc 9f8m7X/NehO/1+DwU1M6NKMGW8CSmRkIVAE9mhFLCG4GalQCU/i3y0GgTPqWVxfxy174 GWTyVWuaCk+WZTyKG4+B1DPrtJmmn8XfiupVTwWV3VN0DwSY/X7I4dxqui6a6M0+5q6b OdRw+goEX1BlFS1xGlA0SC+ihZ64mOVjtSrH5CNpI9oJB9zKWoQoeWOhTmOrhPKMsDYF thqg== X-Gm-Message-State: AOAM533vi/QMyl4xXSQrSqQfAa0E0OUKR9UOgsT5UVTemeEJSHFI33/N qO1h38qZ8d1V5jy7UEEkykKTS6EWGIoApw== X-Google-Smtp-Source: ABdhPJwcOLNM0+g+I9t3WR7WUrpmlaJLqhGHYN2kArxq8xNgS/npCKD7YGlUVx+I+R443rngP4mbaw== X-Received: by 2002:a63:a4c:: with SMTP id z12mr1165590pgk.446.1639738947085; Fri, 17 Dec 2021 03:02:27 -0800 (PST) Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com. [209.85.216.52]) by smtp.gmail.com with ESMTPSA id h4sm9613097pfi.79.2021.12.17.03.02.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Dec 2021 03:02:26 -0800 (PST) Received: by mail-pj1-f52.google.com with SMTP id b1-20020a17090a990100b001b14bd47532so1887888pjp.0; Fri, 17 Dec 2021 03:02:26 -0800 (PST) X-Received: by 2002:a05:6122:104f:: with SMTP id z15mr855694vkn.39.1639738529014; Fri, 17 Dec 2021 02:55:29 -0800 (PST) MIME-Version: 1.0 References: <20211217090248.259122-1-miquel.raynal@bootlin.com> <20211217090248.259122-3-miquel.raynal@bootlin.com> In-Reply-To: From: Geert Uytterhoeven Date: Fri, 17 Dec 2021 11:55:17 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 2/4] mtd: rawnand: rzn1: Add new NAND controller driver To: Wolfram Sang Cc: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , MTD Maling List , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Milan Stevanovic , Jimmy Lalande , Thomas Petazzoni , Linux-Renesas , Magnus Damm , Gareth Williams , Phil Edworthy , Ralph Siemsen , Chris Brandt , Miquel Raynal Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Wolfram, CC Chris Brandt On Fri, Dec 17, 2021 at 11:16 AM Wolfram Sang wrote: > On Fri, Dec 17, 2021 at 10:02:46AM +0100, Miquel Raynal wrote: > > Introduce Renesas RZ/N1x NAND controller driver which supports: > > - All ONFI timing modes > > - Different configurations of its internal ECC controller > > - On-die (not tested) and software ECC support > > - Several chips (not tested) > > - Subpage accesses > > - DMA and PIO > > > > This controller was originally provided by Evatronix before being bought > > by Cadence. > > > > Signed-off-by: Miquel Raynal > > Tested-by: Ralph Siemsen > > This IP core is also available on some Renesas R-Car Gen3 SoCs. I don't > have a board with NAND equipped, so I sadly cannot test your patch and > can only say that the code looks like it is in a really good shape and > can only suggest some renaming. Also on RZ/A2M. RZ/A1 seems to use a different one. Note that RZ/N1 NANDC claims to support up to ONFI2.2, while R-Car Gen3 and RZ/A2M do ONFI1.x only? Chris: usually you are good at IP history ;-) Do you have anything to add? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds