From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 272A4C433E0 for ; Wed, 10 Feb 2021 14:21:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D4BB964E7A for ; Wed, 10 Feb 2021 14:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230376AbhBJOV5 (ORCPT ); Wed, 10 Feb 2021 09:21:57 -0500 Received: from mail-ot1-f44.google.com ([209.85.210.44]:39424 "EHLO mail-ot1-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230328AbhBJOV4 (ORCPT ); Wed, 10 Feb 2021 09:21:56 -0500 Received: by mail-ot1-f44.google.com with SMTP id d7so1896961otq.6; Wed, 10 Feb 2021 06:21:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=QWv25sZTzfQsa6EKZRYZsW4Xzm4uyOUtOgHrp6KoZsw=; b=ooalySMRcwom6fuadO+5m2/ehhVisTMnZ7MCYkhU/o0EK1rrYcavF4A7ZslOoTt1mC h2bUDTBU1oyak2bNPmVSqNEYFX/gv73znAA6ok6UNFduxCB1Mcay58F55yj6WVr9biTQ 0RiqWaGLmFcpprsgEyl77cQrJcQ+gBwegczNk4BQHxP/29EtJHRUeO4MbKPrZvWZtTFt coSVb82uogkGDY36RKxPCg4y1AnLvm3dsdEj+JklRMdu/LWloYujvygjWY8wfbWuMR1k fAg1okWOCbl4PNNMByzDhgHs3xnXosNJXo+aoiLQFihAaRK/loJbS35x8iugNo2DEwF1 e6Vg== X-Gm-Message-State: AOAM531F5iGzYAbWQrx567osCbuuCwN3zWugqqmPh06Fezv5WjWGG52U TdTKAIXw0ZWsVOedEXYvUq1Z/5rUDDdj4CiS2RI= X-Google-Smtp-Source: ABdhPJyHmgLG/wJNJM+uoRRAPNtNaZj+QytW6s4cvQKIGCjtm/DCckSOggT59JBOjwi2k9kpLrwL4qRlWYNL6TEuW38= X-Received: by 2002:a9d:77d6:: with SMTP id w22mr2245205otl.145.1612966875162; Wed, 10 Feb 2021 06:21:15 -0800 (PST) MIME-Version: 1.0 References: <20210210132751.1422386-1-geert+renesas@glider.be> <87mtwcujd0.fsf@microchip.com> <20210210141728.GO351084@piout.net> In-Reply-To: <20210210141728.GO351084@piout.net> From: Geert Uytterhoeven Date: Wed, 10 Feb 2021 15:21:04 +0100 Message-ID: Subject: Re: [PATCH] pinctrl: PINCTRL_MICROCHIP_SGPIO should depend on ARCH_SPARX5 || SOC_VCOREIII To: Alexandre Belloni Cc: Lars Povlsen , Linus Walleij , Steen Hegelund , Microchip Linux Driver Support , "open list:GPIO SUBSYSTEM" , Linux ARM , "open list:BROADCOM NVRAM DRIVER" , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Alexandre, On Wed, Feb 10, 2021 at 3:17 PM Alexandre Belloni wrote: > On 10/02/2021 14:53:01+0100, Geert Uytterhoeven wrote: > > On Wed, Feb 10, 2021 at 2:45 PM Lars Povlsen wrote: > > > Geert Uytterhoeven writes: > > > > the Microsemi/Microchip Serial GPIO device is present only Microsemi > > > > VCore III and Microchip Sparx5 SoCs. Hence add a dependency on > > > > ARCH_SPARX5 || SOC_VCOREIII, to prevent asking the user about this > > > > driver when configuring a kernel without support for these SoCs. > > > > > > > > Fixes: 7e5ea974e61c8dd0 ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO") > > > > Signed-off-by: Geert Uytterhoeven > > > > --- > > > > drivers/pinctrl/Kconfig | 4 ++-- > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig > > > > index 113073d5f89bbf70..3b75b1d7d3d1f1b0 100644 > > > > --- a/drivers/pinctrl/Kconfig > > > > +++ b/drivers/pinctrl/Kconfig > > > > @@ -353,8 +353,8 @@ config PINCTRL_OCELOT > > > > > > > > config PINCTRL_MICROCHIP_SGPIO > > > > bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" > > > > - depends on OF > > > > - depends on HAS_IOMEM > > > > + depends on OF && HAS_IOMEM > > > > + depends on ARCH_SPARX5 || SOC_VCOREIII || COMPILE_TEST > > > > select GPIOLIB > > > > select GPIOLIB_IRQCHIP > > > > select GENERIC_PINCONF > > > > > > Thank you for your patch. Unfortunately, it makes it impossible to use > > > the driver across PCIe - which is a specifically desired configuration. > > > > > > Could you add CONFIG_PCI to the || chain? > > > > Sure. > > > > Is PCIe the only other transport over which the register can be accessed? > > Or can this also be done over e.g. SPI, like on Ocelot[1]? > > > > [1] https://lore.kernel.org/linux-gpio/20200511145329.GV34497@piout.net/ > > > > Yes, this driver IP is also available on Ocelot (this is SOC_VCOREIII) > so this is also available over SPI. Hence would you consider depends on ARCH_SPARX5 || SOC_VCOREIII || PCI || SPI || COMPILE_TEST acceptable? Or would that be futile, as must systems have PCI and/or SPI enabled anyway? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71014C433E0 for ; Wed, 10 Feb 2021 14:22:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2053164E77 for ; Wed, 10 Feb 2021 14:22:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2053164E77 Authentication-Results: mail.kernel.org; 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Wed, 10 Feb 2021 06:21:15 -0800 (PST) MIME-Version: 1.0 References: <20210210132751.1422386-1-geert+renesas@glider.be> <87mtwcujd0.fsf@microchip.com> <20210210141728.GO351084@piout.net> In-Reply-To: <20210210141728.GO351084@piout.net> From: Geert Uytterhoeven Date: Wed, 10 Feb 2021 15:21:04 +0100 Message-ID: Subject: Re: [PATCH] pinctrl: PINCTRL_MICROCHIP_SGPIO should depend on ARCH_SPARX5 || SOC_VCOREIII To: Alexandre Belloni X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210210_092117_268989_E763023A X-CRM114-Status: GOOD ( 27.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux Kernel Mailing List , Linus Walleij , "open list:BROADCOM NVRAM DRIVER" , Microchip Linux Driver Support , "open list:GPIO SUBSYSTEM" , Lars Povlsen , Steen Hegelund , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Alexandre, On Wed, Feb 10, 2021 at 3:17 PM Alexandre Belloni wrote: > On 10/02/2021 14:53:01+0100, Geert Uytterhoeven wrote: > > On Wed, Feb 10, 2021 at 2:45 PM Lars Povlsen wrote: > > > Geert Uytterhoeven writes: > > > > the Microsemi/Microchip Serial GPIO device is present only Microsemi > > > > VCore III and Microchip Sparx5 SoCs. Hence add a dependency on > > > > ARCH_SPARX5 || SOC_VCOREIII, to prevent asking the user about this > > > > driver when configuring a kernel without support for these SoCs. > > > > > > > > Fixes: 7e5ea974e61c8dd0 ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO") > > > > Signed-off-by: Geert Uytterhoeven > > > > --- > > > > drivers/pinctrl/Kconfig | 4 ++-- > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig > > > > index 113073d5f89bbf70..3b75b1d7d3d1f1b0 100644 > > > > --- a/drivers/pinctrl/Kconfig > > > > +++ b/drivers/pinctrl/Kconfig > > > > @@ -353,8 +353,8 @@ config PINCTRL_OCELOT > > > > > > > > config PINCTRL_MICROCHIP_SGPIO > > > > bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" > > > > - depends on OF > > > > - depends on HAS_IOMEM > > > > + depends on OF && HAS_IOMEM > > > > + depends on ARCH_SPARX5 || SOC_VCOREIII || COMPILE_TEST > > > > select GPIOLIB > > > > select GPIOLIB_IRQCHIP > > > > select GENERIC_PINCONF > > > > > > Thank you for your patch. Unfortunately, it makes it impossible to use > > > the driver across PCIe - which is a specifically desired configuration. > > > > > > Could you add CONFIG_PCI to the || chain? > > > > Sure. > > > > Is PCIe the only other transport over which the register can be accessed? > > Or can this also be done over e.g. SPI, like on Ocelot[1]? > > > > [1] https://lore.kernel.org/linux-gpio/20200511145329.GV34497@piout.net/ > > > > Yes, this driver IP is also available on Ocelot (this is SOC_VCOREIII) > so this is also available over SPI. Hence would you consider depends on ARCH_SPARX5 || SOC_VCOREIII || PCI || SPI || COMPILE_TEST acceptable? Or would that be futile, as must systems have PCI and/or SPI enabled anyway? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel