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[209.85.219.181]) by smtp.gmail.com with ESMTPSA id t10-20020a37ea0a000000b006a8b6848556sm4669326qkj.7.2022.06.17.08.16.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Jun 2022 08:16:10 -0700 (PDT) Received: by mail-yb1-f181.google.com with SMTP id n144so3724473ybf.12; Fri, 17 Jun 2022 08:16:10 -0700 (PDT) X-Received: by 2002:a25:818c:0:b0:664:a584:fafd with SMTP id p12-20020a25818c000000b00664a584fafdmr11150422ybk.543.1655478970399; Fri, 17 Jun 2022 08:16:10 -0700 (PDT) MIME-Version: 1.0 References: <874k0nlrbw.wl-kuninori.morimoto.gx@renesas.com> <87y1xzkcq0.wl-kuninori.morimoto.gx@renesas.com> In-Reply-To: <87y1xzkcq0.wl-kuninori.morimoto.gx@renesas.com> From: Geert Uytterhoeven Date: Fri, 17 Jun 2022 17:15:59 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions To: Kuninori Morimoto Cc: Linus Walleij , Linux-Renesas , "open list:GPIO SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Morimoto-san, On Tue, Jun 14, 2022 at 7:58 AM Kuninori Morimoto wrote: > From: Phong Hoang > > This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI, > MSIOF, PWM, CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions > > [Morimoto merged above patches into one, cleanup white space, > sort modules alphabetically, fixup comments] > Signed-off-by: Phong Hoang > Signed-off-by: Hai Pham > Signed-off-by: Thanh Quan > Signed-off-by: CongDang > Signed-off-by: Kazuya Mizuguch > Signed-off-by: Tho Vu > Signed-off-by: Kuninori Morimoto Thanks for your patch! > --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c > +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c > +/* - SCIF0 ------------------------------------------------------------------ */ > +static const unsigned int scif0_data_pins[] = { > + /* RX0, TX0 */ > + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12), > +}; > +static const unsigned int scif0_data_mux[] = { > + RX0_MARK, TX0_MARK, > +}; > +static const unsigned int scif0_clk_pins[] = { > + /* SCK0 */ > + RCAR_GP_PIN(1, 15), > +}; > +static const unsigned int scif0_clk_mux[] = { > + SCK0_MARK, > +}; > +static const unsigned int scif0_ctrl_pins[] = { > + /* RTS0#, CTS0# */ > + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), > +}; > +static const unsigned int scif0_ctrl_mux[] = { > + RTS0_N_MARK, CTS0_N_MARK, > +}; > + > +/* - SCIF1 ------------------------------------------------------------------ */ > +static const unsigned int scif1_data_pins[] = { > + /* RX1, TX1 */ > + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), > +}; > +static const unsigned int scif1_data_mux[] = { > + RX1_MARK, TX1_MARK, > +}; > +static const unsigned int scif1_clk_pins[] = { > + /* SCK1 */ > + RCAR_GP_PIN(0, 18), > +}; > +static const unsigned int scif1_clk_mux[] = { > + SCK1_MARK, > +}; > +static const unsigned int scif1_ctrl_pins[] = { > + /* RTS1_N, CTS1_N */ Compared to v2, you changed: -+ /* RTS1#, CTS1# */ ++ /* RTS1_N, CTS1_N */ (same for SCIF3). While this makes sense, as all but the *_pins[] comments use "_N" instead of "#", it does make SCIF1/SCIF3 inconsistent with the other (H)SCIF ports, here and in later patches. > + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), > +}; > +static const unsigned int scif1_ctrl_mux[] = { > + RTS1_N_MARK, CTS1_N_MARK, > +}; > + > +/* - SCIF3 ------------------------------------------------------------------ */ > +static const unsigned int scif3_data_pins[] = { > + /* RX3, TX3 */ > + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), > +}; > +static const unsigned int scif3_data_mux[] = { > + RX3_MARK, TX3_MARK, > +}; > +static const unsigned int scif3_clk_pins[] = { > + /* SCK3 */ > + RCAR_GP_PIN(1, 4), > +}; > +static const unsigned int scif3_clk_mux[] = { > + SCK3_MARK, > +}; > +static const unsigned int scif3_ctrl_pins[] = { > + /* RTS3_N, CTS3_N */ > + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), > +}; > +static const unsigned int scif3_ctrl_mux[] = { > + RTS3_N_MARK, CTS3_N_MARK, > +}; > + > +/* - SCIF4 ------------------------------------------------------------------ */ > +static const unsigned int scif4_data_pins[] = { > + /* RX4, TX4 */ > + RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12), > +}; > +static const unsigned int scif4_data_mux[] = { > + RX4_MARK, TX4_MARK, > +}; > +static const unsigned int scif4_clk_pins[] = { > + /* SCK4 */ > + RCAR_GP_PIN(8, 8), > +}; > +static const unsigned int scif4_clk_mux[] = { > + SCK4_MARK, > +}; > +static const unsigned int scif4_ctrl_pins[] = { > + /* RTS4#, CTS4# */ > + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9), > +}; > +static const unsigned int scif4_ctrl_mux[] = { > + RTS4_N_MARK, CTS4_N_MARK, > +}; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds