[PATCH 0/3] pinctrl: sh-pfc: add r8a7795 support for voltage switching

[PATCH 0/3] pinctrl: sh-pfc: add r8a7795 support for voltage switching

[Wolfram Sang]

This series adds support for PFC voltage switching for r8a7795. I decided to
refactor voltage switching because all Gen2 and Gen3 hardware follow the same
style to do that. So, we can put generic handling to the core and keep only
pin-to-bit mapping SoC specific. See patch 1 for details.

Tested on a Lager board (r8a7790/H2) and a Salvator-X (r8a7795/H3) by using
UHS/non-UHS SD cards. They work fine with SDR50 and the POCCTRL register
setting was also verified.

Branch is here:

git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/topic/h3-pfc-set-voltage

Changes since RFC:
* be precise in encoding which pins can do voltage switching on bank3
* addded Geert's reviewed tag (thanks!)

Please apply,

   Wolfram

Wolfram Sang (3):
  pinctrl: sh-pfc: refactor voltage setting
  pinctrl: sh-pfc: r8a7795: add support for voltage switching
  arm64: dts: r8a7795: salvator: enable UHS for SDHI 0 & 3

 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 22 +++++++-
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c               | 58 +++++-----------------
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c               | 28 ++++++++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   | 41 +++++++++------
 drivers/pinctrl/sh-pfc/sh_pfc.h                    |  4 +-
 5 files changed, 86 insertions(+), 67 deletions(-)

-- 
2.8.1

[PATCH 1/3] pinctrl: sh-pfc: refactor voltage setting

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

All known hardware being able to switch voltages has the same POCCTRL
register. So, factor out the common code to the core and keep only
the pin-to-bit mapping SoC specific. Convert the only user, r8a7790.
In case POCCTRL should ever get more complex (more voltages to select?),
we should probably switch over to a describing array like drive strength
does currently.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 58 ++++++++----------------------------
 drivers/pinctrl/sh-pfc/pinctrl.c     | 41 +++++++++++++++----------
 drivers/pinctrl/sh-pfc/sh_pfc.h      |  4 +--
 3 files changed, 40 insertions(+), 63 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index eed8daa464cc1e..1537a077939977 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -4696,47 +4696,6 @@ static const char * const vin3_groups[] = {
 	"vin3_clk",
 };
 
-#define IOCTRL6 0x8c
-
-static int r8a7790_get_io_voltage(struct sh_pfc *pfc, unsigned int pin)
-{
-	u32 data, mask;
-
-	if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
-		return -EINVAL;
-
-	data = ioread32(pfc->windows->virt + IOCTRL6),
-	/* Bits in IOCTRL6 are numbered in opposite order to pins */
-	mask = 0x80000000 >> (pin & 0x1f);
-
-	return (data & mask) ? 3300 : 1800;
-}
-
-static int r8a7790_set_io_voltage(struct sh_pfc *pfc, unsigned int pin, u16 mV)
-{
-	u32 data, mask;
-
-	if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
-		return -EINVAL;
-
-	if (mV != 1800 && mV != 3300)
-		return -EINVAL;
-
-	data = ioread32(pfc->windows->virt + IOCTRL6);
-	/* Bits in IOCTRL6 are numbered in opposite order to pins */
-	mask = 0x80000000 >> (pin & 0x1f);
-
-	if (mV == 3300)
-		data |= mask;
-	else
-		data &= ~mask;
-
-	iowrite32(~data, pfc->windows->virt); /* unlock reg */
-	iowrite32(data, pfc->windows->virt + IOCTRL6);
-
-	return 0;
-}
-
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(audio_clk),
 	SH_PFC_FUNCTION(avb),
@@ -5736,14 +5695,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 	{ },
 };
 
-static const struct sh_pfc_soc_operations pinmux_ops = {
-	.get_io_voltage = r8a7790_get_io_voltage,
-	.set_io_voltage = r8a7790_set_io_voltage,
+static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+	if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
+		return -EINVAL;
+
+	*pocctrl = 0xe606008c;
+
+	return 31 - (pin & 0x1f);
+}
+
+static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
+	.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
 };
 
 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
 	.name = "r8a77900_pfc",
-	.ops = &pinmux_ops,
+	.ops = &r8a7790_pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index fdb445d68b9a08..d4e65bc7dacd67 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -632,19 +632,21 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
 	}
 
 	case PIN_CONFIG_POWER_SOURCE: {
-		int ret;
+		u32 pocctrl, val;
+		int bit;
 
-		if (!pfc->info->ops || !pfc->info->ops->get_io_voltage)
+		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 			return -ENOTSUPP;
 
+		bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
+		if (WARN(bit < 0, "invalid pin %#x", _pin))
+			return bit;
+
 		spin_lock_irqsave(&pfc->lock, flags);
-		ret = pfc->info->ops->get_io_voltage(pfc, _pin);
+		val = sh_pfc_read_reg(pfc, pocctrl, 32);
 		spin_unlock_irqrestore(&pfc->lock, flags);
 
-		if (ret < 0)
-			return ret;
-
-		*config = ret;
+		*config = (val & BIT(bit)) ? 3300 : 1800;
 		break;
 	}
 
@@ -696,20 +698,29 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
 		}
 
 		case PIN_CONFIG_POWER_SOURCE: {
-			unsigned int arg =
-				pinconf_to_config_argument(configs[i]);
-			int ret;
+			unsigned int mV = pinconf_to_config_argument(configs[i]);
+			u32 pocctrl, val;
+			int bit;
 
-			if (!pfc->info->ops || !pfc->info->ops->set_io_voltage)
+			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 				return -ENOTSUPP;
 
+			bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
+			if (WARN(bit < 0, "invalid pin %#x", _pin))
+				return bit;
+
+			if (mV != 1800 && mV != 3300)
+				return -EINVAL;
+
 			spin_lock_irqsave(&pfc->lock, flags);
-			ret = pfc->info->ops->set_io_voltage(pfc, _pin, arg);
+			val = sh_pfc_read_reg(pfc, pocctrl, 32);
+			if (mV == 3300)
+				val |= BIT(bit);
+			else
+				val &= ~BIT(bit);
+			sh_pfc_write_reg(pfc, pocctrl, 32, val);
 			spin_unlock_irqrestore(&pfc->lock, flags);
 
-			if (ret)
-				return ret;
-
 			break;
 		}
 
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 656ea32f776c92..ea3a527514558a 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -189,9 +189,7 @@ struct sh_pfc_soc_operations {
 	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
 	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
 			 unsigned int bias);
-	int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
-	int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
-			      u16 voltage_mV);
+	int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
 };
 
 struct sh_pfc_soc_info {
-- 
2.8.1

[PATCH 2/3] pinctrl: sh-pfc: r8a7795: add support for voltage switching

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 44632b1a5c978c..33be5d56e3162a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -17,8 +17,12 @@
 	PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
 	PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
 	PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
-	PORT_GP_CFG_16(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
-	PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+	PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
+	PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+	PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+	PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+	PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
+	PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
 	PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
 	PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
 	PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
@@ -4765,8 +4769,28 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
 	{ },
 };
 
+static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+	int bit = -EINVAL;
+
+	*pocctrl = 0xe6060380;
+
+	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+		bit = pin & 0x1f;
+
+	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
+		bit = (pin & 0x1f) + 12;
+
+	return bit;
+}
+
+static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
+	.pin_to_pocctrl = r8a7795_pin_to_pocctrl,
+};
+
 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
 	.name = "r8a77950_pfc",
+	.ops = &r8a7795_pinmux_ops,
 	.unlock_reg = 0xe6060000, /* PMMR */
 
 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-- 
2.8.1

[PATCH 3/3] arm64: dts: r8a7795: salvator: enable UHS for SDHI 0 & 3

[Wolfram Sang]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index abb25cfc20bd57..726426693f1fa0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -229,11 +229,25 @@
 	sdhi0_pins: sd0 {
 		groups = "sdhi0_data4", "sdhi0_ctrl";
 		function = "sdhi0";
+		power-source = <3300>;
+	};
+
+	sdhi0_pins_uhs: sd0_uhs {
+		groups = "sdhi0_data4", "sdhi0_ctrl";
+		function = "sdhi0";
+		power-source = <1800>;
 	};
 
 	sdhi3_pins: sd3 {
 		groups = "sdhi3_data4", "sdhi3_ctrl";
 		function = "sdhi3";
+		power-source = <3300>;
+	};
+
+	sdhi3_pins_uhs: sd3_uhs {
+		groups = "sdhi3_data4", "sdhi3_ctrl";
+		function = "sdhi3";
+		power-source = <1800>;
 	};
 
 	sound_pins: sound {
@@ -374,25 +388,29 @@
 
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdhi0_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
 
 	vmmc-supply = <&vcc_sdhi0>;
 	vqmmc-supply = <&vccq_sdhi0>;
 	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 	bus-width = <4>;
+	sd-uhs-sdr50;
 	status = "okay";
 };
 
 &sdhi3 {
 	pinctrl-0 = <&sdhi3_pins>;
-	pinctrl-names = "default";
+	pinctrl-1 = <&sdhi3_pins_uhs>;
+	pinctrl-names = "default", "state_uhs";
 
 	vmmc-supply = <&vcc_sdhi3>;
 	vqmmc-supply = <&vccq_sdhi3>;
 	cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 	bus-width = <4>;
+	sd-uhs-sdr50;
 	status = "okay";
 };
 
-- 
2.8.1

Re: [PATCH 0/3] pinctrl: sh-pfc: add r8a7795 support for voltage switching

[Geert Uytterhoeven]

Hi Wolfram,

On Mon, Jun 6, 2016 at 6:08 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> This series adds support for PFC voltage switching for r8a7795. I decided to
> refactor voltage switching because all Gen2 and Gen3 hardware follow the same
> style to do that. So, we can put generic handling to the core and keep only
> pin-to-bit mapping SoC specific. See patch 1 for details.
>
> Tested on a Lager board (r8a7790/H2) and a Salvator-X (r8a7795/H3) by using
> UHS/non-UHS SD cards. They work fine with SDR50 and the POCCTRL register
> setting was also verified.
>
> Branch is here:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/topic/h3-pfc-set-voltage
>
> Changes since RFC:
> * be precise in encoding which pins can do voltage switching on bank3
> * addded Geert's reviewed tag (thanks!)
>
> Please apply,
>
>    Wolfram
>
> Wolfram Sang (3):
>   pinctrl: sh-pfc: refactor voltage setting
>   pinctrl: sh-pfc: r8a7795: add support for voltage switching
>   arm64: dts: r8a7795: salvator: enable UHS for SDHI 0 & 3

Thanks for your series!

I've queued the first two patches in sh-pfc-for-v4.8, and will send a pull
request after next renesas-drivers release.

BTW, are these a hard dependency for patch 3, or will the missing power
source control just be ignored?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 0/3] pinctrl: sh-pfc: add r8a7795 support for voltage switching

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 338 bytes --]


> BTW, are these a hard dependency for patch 3, or will the missing power
> source control just be ignored?

Long answer short: It is a hard dependency.

It shouldn't be, but fixing this might need patches to pfc, mmc-core,
and sdhi driver. Need to think about it. (and even then, patch 3 will be
depending on these yet-to-come fixes).


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

Re: [PATCH 0/3] pinctrl: sh-pfc: add r8a7795 support for voltage switching

[Geert Uytterhoeven]

Hi Wolfram,

On Fri, Jun 10, 2016 at 1:12 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
>> BTW, are these a hard dependency for patch 3, or will the missing power
>> source control just be ignored?
>
> Long answer short: It is a hard dependency.
>
> It shouldn't be, but fixing this might need patches to pfc, mmc-core,
> and sdhi driver. Need to think about it. (and even then, patch 3 will be
> depending on these yet-to-come fixes).

Thanks, good to know! ;-)

Simon: So either you can merge sh-pfc-for-v4.8 first (after I have sent the
pull request, and Linus W. has merged it!), or the DTS update will have to wait
for v4.9.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 0/3] pinctrl: sh-pfc: add r8a7795 support for voltage switching

[Simon Horman]

On Fri, Jun 10, 2016 at 01:21:39PM +0200, Geert Uytterhoeven wrote:
> Hi Wolfram,
> 
> On Fri, Jun 10, 2016 at 1:12 PM, Wolfram Sang <wsa@the-dreams.de> wrote:
> >> BTW, are these a hard dependency for patch 3, or will the missing power
> >> source control just be ignored?
> >
> > Long answer short: It is a hard dependency.
> >
> > It shouldn't be, but fixing this might need patches to pfc, mmc-core,
> > and sdhi driver. Need to think about it. (and even then, patch 3 will be
> > depending on these yet-to-come fixes).
> 
> Thanks, good to know! ;-)
> 
> Simon: So either you can merge sh-pfc-for-v4.8 first (after I have sent the
> pull request, and Linus W. has merged it!), or the DTS update will have to wait
> for v4.9.

I prefer to wait to v4.9 unless there is a good reason no to.

Re: [PATCH 3/3] arm64: dts: r8a7795: salvator: enable UHS for SDHI 0 & 3

[Dirk Behme]

Hi Wolfram,

On 06.06.2016 18:08, Wolfram Sang wrote:
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
> index abb25cfc20bd57..726426693f1fa0 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
> @@ -229,11 +229,25 @@
>  	sdhi0_pins: sd0 {
>  		groups = "sdhi0_data4", "sdhi0_ctrl";
>  		function = "sdhi0";
> +		power-source = <3300>;
> +	};
> +
> +	sdhi0_pins_uhs: sd0_uhs {
> +		groups = "sdhi0_data4", "sdhi0_ctrl";
> +		function = "sdhi0";
> +		power-source = <1800>;
>  	};
>
>  	sdhi3_pins: sd3 {
>  		groups = "sdhi3_data4", "sdhi3_ctrl";
>  		function = "sdhi3";
> +		power-source = <3300>;
> +	};
> +
> +	sdhi3_pins_uhs: sd3_uhs {
> +		groups = "sdhi3_data4", "sdhi3_ctrl";
> +		function = "sdhi3";
> +		power-source = <1800>;
>  	};
>
>  	sound_pins: sound {
> @@ -374,25 +388,29 @@
>
>  &sdhi0 {
>  	pinctrl-0 = <&sdhi0_pins>;
> -	pinctrl-names = "default";
> +	pinctrl-1 = <&sdhi0_pins_uhs>;
> +	pinctrl-names = "default", "state_uhs";
>
>  	vmmc-supply = <&vcc_sdhi0>;
>  	vqmmc-supply = <&vccq_sdhi0>;
>  	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
>  	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
>  	bus-width = <4>;
> +	sd-uhs-sdr50;
>  	status = "okay";
>  };
>
>  &sdhi3 {
>  	pinctrl-0 = <&sdhi3_pins>;
> -	pinctrl-names = "default";
> +	pinctrl-1 = <&sdhi3_pins_uhs>;
> +	pinctrl-names = "default", "state_uhs";
>
>  	vmmc-supply = <&vcc_sdhi3>;
>  	vqmmc-supply = <&vccq_sdhi3>;
>  	cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
>  	wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
>  	bus-width = <4>;
> +	sd-uhs-sdr50;
>  	status = "okay";
>  };


Could you kindly share the recent status of the MMC support for RCar3? 
Esp. the eMMC support on the Salvator-X? From time to time I get this 
question from several people ;)


Best regards

Dirk

Re: [PATCH 3/3] arm64: dts: r8a7795: salvator: enable UHS for SDHI 0 & 3

[Wolfram Sang]

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> Could you kindly share the recent status of the MMC support for RCar3? Esp.
> the eMMC support on the Salvator-X? From time to time I get this question
> from several people ;)

Nothing changed since last time. Meaning that it could work in 4-bit
mode (haven't tested it, though, and am on the road right now), it
probably won't with 8-bit.


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