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* [PATCH 0/5] Add I2C4/DU0/QSPI0/SDHI2/USB to r8a77470
@ 2018-09-18 13:47 Fabrizio Castro
  2018-09-18 13:47 ` [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups Fabrizio Castro
                   ` (4 more replies)
  0 siblings, 5 replies; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-18 13:47 UTC (permalink / raw)
  To: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij
  Cc: Fabrizio Castro, linux-renesas-soc, linux-gpio, Simon Horman,
	Chris Paterson, Biju Das

Dear All,

this series adds I2C4/DU0/QSPI0/SDHI2/USB0/USB1 pin groups and
functions to the RZ/G1C (a.k.a. r8a77470).

Thanks,
Fab

Fabrizio Castro (5):
  pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
  pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
  pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
  pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  pinctrl: sh-pfc: r8a77470: Add USB pin groups

 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 275 ++++++++++++++++++++++++++++++++++
 1 file changed, 275 insertions(+)

-- 
2.7.4

^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
  2018-09-18 13:47 [PATCH 0/5] Add I2C4/DU0/QSPI0/SDHI2/USB to r8a77470 Fabrizio Castro
@ 2018-09-18 13:47 ` Fabrizio Castro
  2018-09-19  8:57   ` Geert Uytterhoeven
  2018-09-18 13:47 ` [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 " Fabrizio Castro
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-18 13:47 UTC (permalink / raw)
  To: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij
  Cc: Fabrizio Castro, linux-renesas-soc, linux-gpio, Simon Horman,
	Chris Paterson, Biju Das

Add I2C4 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 51 +++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index 995c959..d4de404 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -1197,6 +1197,42 @@ static const unsigned int avb_avtp_capture_b_pins[] = {
 static const unsigned int avb_avtp_capture_b_mux[] = {
 	AVB_AVTP_CAPTURE_B_MARK,
 };
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_a_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int i2c4_a_mux[] = {
+	SCL4_A_MARK, SDA4_A_MARK,
+};
+static const unsigned int i2c4_b_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
+};
+static const unsigned int i2c4_b_mux[] = {
+	SCL4_B_MARK, SDA4_B_MARK,
+};
+static const unsigned int i2c4_c_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
+};
+static const unsigned int i2c4_c_mux[] = {
+	SCL4_C_MARK, SDA4_C_MARK,
+};
+static const unsigned int i2c4_d_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+};
+static const unsigned int i2c4_d_mux[] = {
+	SCL4_D_MARK, SDA4_D_MARK,
+};
+static const unsigned int i2c4_e_pins[] = {
+	/* SCL, SDA */
+	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int i2c4_e_mux[] = {
+	SCL4_E_MARK, SDA4_E_MARK,
+};
 /* - MMC -------------------------------------------------------------------- */
 static const unsigned int mmc_data1_pins[] = {
 	/* D0 */
@@ -1487,6 +1523,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+	SH_PFC_PIN_GROUP(i2c4_a),
+	SH_PFC_PIN_GROUP(i2c4_b),
+	SH_PFC_PIN_GROUP(i2c4_c),
+	SH_PFC_PIN_GROUP(i2c4_d),
+	SH_PFC_PIN_GROUP(i2c4_e),
 	SH_PFC_PIN_GROUP(mmc_data1),
 	SH_PFC_PIN_GROUP(mmc_data4),
 	SH_PFC_PIN_GROUP(mmc_data8),
@@ -1541,6 +1582,15 @@ static const char * const avb_groups[] = {
 	"avb_avtp_match_b",
 	"avb_avtp_capture_b",
 };
+
+static const char * const i2c4_groups[] = {
+	"i2c4_a",
+	"i2c4_b",
+	"i2c4_c",
+	"i2c4_d",
+	"i2c4_e",
+};
+
 static const char * const mmc_groups[] = {
 	"mmc_data1",
 	"mmc_data4",
@@ -1604,6 +1654,7 @@ static const char * const scif_clk_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(avb),
+	SH_PFC_FUNCTION(i2c4),
 	SH_PFC_FUNCTION(mmc),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
  2018-09-18 13:47 [PATCH 0/5] Add I2C4/DU0/QSPI0/SDHI2/USB to r8a77470 Fabrizio Castro
  2018-09-18 13:47 ` [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups Fabrizio Castro
@ 2018-09-18 13:47 ` Fabrizio Castro
  2018-09-19  9:07   ` Geert Uytterhoeven
  2018-09-18 13:47 ` [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 " Fabrizio Castro
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-18 13:47 UTC (permalink / raw)
  To: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij
  Cc: Fabrizio Castro, linux-renesas-soc, linux-gpio, Simon Horman,
	Chris Paterson, Biju Das

Add DU0 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 109 ++++++++++++++++++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index d4de404..a16a010 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -1197,6 +1197,93 @@ static const unsigned int avb_avtp_capture_b_pins[] = {
 static const unsigned int avb_avtp_capture_b_mux[] = {
 	AVB_AVTP_CAPTURE_B_MARK,
 };
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du0_rgb666_pins[] = {
+	/* R[7:2], G[7:2], B[7:2] */
+	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
+	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
+	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
+	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
+};
+static const unsigned int du0_rgb666_mux[] = {
+	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+	DU0_DR3_MARK, DU0_DR2_MARK,
+	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+	DU0_DG3_MARK, DU0_DG2_MARK,
+	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+	DU0_DB3_MARK, DU0_DB2_MARK,
+};
+static const unsigned int du0_rgb888_pins[] = {
+	/* R[7:0], G[7:0], B[7:0] */
+	RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
+	RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
+	RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
+	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
+	RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
+	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
+	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
+	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
+};
+static const unsigned int du0_rgb888_mux[] = {
+	DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+	DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
+	DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+	DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
+	DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+	DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
+};
+static const unsigned int du0_clk0_out_pins[] = {
+	/* DOTCLKOUT0 */
+	RCAR_GP_PIN(2, 25),
+};
+static const unsigned int du0_clk0_out_mux[] = {
+	DU0_DOTCLKOUT0_MARK
+};
+static const unsigned int du0_clk1_out_pins[] = {
+	/* DOTCLKOUT1 */
+	RCAR_GP_PIN(2, 26),
+};
+static const unsigned int du0_clk1_out_mux[] = {
+	DU0_DOTCLKOUT1_MARK
+};
+static const unsigned int du0_clk_in_pins[] = {
+	/* CLKIN */
+	RCAR_GP_PIN(2, 24),
+};
+static const unsigned int du0_clk_in_mux[] = {
+	DU0_DOTCLKIN_MARK
+};
+static const unsigned int du0_sync_pins[] = {
+	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+	RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
+};
+static const unsigned int du0_sync_mux[] = {
+	DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
+};
+static const unsigned int du0_oddf_pins[] = {
+	/* EXODDF/ODDF/DISP/CDE */
+	RCAR_GP_PIN(2, 29),
+};
+static const unsigned int du0_oddf_mux[] = {
+	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
+};
+static const unsigned int du0_cde_pins[] = {
+	/* CDE */
+	RCAR_GP_PIN(2, 31),
+};
+static const unsigned int du0_cde_mux[] = {
+	DU0_CDE_MARK,
+};
+static const unsigned int du0_disp_pins[] = {
+	/* DISP */
+	RCAR_GP_PIN(2, 30),
+};
+static const unsigned int du0_disp_mux[] = {
+	DU0_DISP_MARK
+};
 /* - I2C4 ------------------------------------------------------------------- */
 static const unsigned int i2c4_a_pins[] = {
 	/* SCL, SDA */
@@ -1523,6 +1610,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(avb_avtp_capture_a),
 	SH_PFC_PIN_GROUP(avb_avtp_match_b),
 	SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+	SH_PFC_PIN_GROUP(du0_rgb666),
+	SH_PFC_PIN_GROUP(du0_rgb888),
+	SH_PFC_PIN_GROUP(du0_clk0_out),
+	SH_PFC_PIN_GROUP(du0_clk1_out),
+	SH_PFC_PIN_GROUP(du0_clk_in),
+	SH_PFC_PIN_GROUP(du0_sync),
+	SH_PFC_PIN_GROUP(du0_oddf),
+	SH_PFC_PIN_GROUP(du0_cde),
+	SH_PFC_PIN_GROUP(du0_disp),
 	SH_PFC_PIN_GROUP(i2c4_a),
 	SH_PFC_PIN_GROUP(i2c4_b),
 	SH_PFC_PIN_GROUP(i2c4_c),
@@ -1583,6 +1679,18 @@ static const char * const avb_groups[] = {
 	"avb_avtp_capture_b",
 };
 
+static const char * const du0_groups[] = {
+	"du0_rgb666",
+	"du0_rgb888",
+	"du0_clk0_out",
+	"du0_clk1_out",
+	"du0_clk_in",
+	"du0_sync",
+	"du0_oddf",
+	"du0_cde",
+	"du0_disp",
+};
+
 static const char * const i2c4_groups[] = {
 	"i2c4_a",
 	"i2c4_b",
@@ -1654,6 +1762,7 @@ static const char * const scif_clk_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(avb),
+	SH_PFC_FUNCTION(du0),
 	SH_PFC_FUNCTION(i2c4),
 	SH_PFC_FUNCTION(mmc),
 	SH_PFC_FUNCTION(scif0),
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
  2018-09-18 13:47 [PATCH 0/5] Add I2C4/DU0/QSPI0/SDHI2/USB to r8a77470 Fabrizio Castro
  2018-09-18 13:47 ` [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups Fabrizio Castro
  2018-09-18 13:47 ` [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 " Fabrizio Castro
@ 2018-09-18 13:47 ` Fabrizio Castro
  2018-09-19  9:16   ` Geert Uytterhoeven
  2018-09-18 13:47 ` [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 " Fabrizio Castro
  2018-09-18 13:47 ` [PATCH 5/5] pinctrl: sh-pfc: r8a77470: Add USB " Fabrizio Castro
  4 siblings, 1 reply; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-18 13:47 UTC (permalink / raw)
  To: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij
  Cc: Fabrizio Castro, linux-renesas-soc, linux-gpio, Simon Horman,
	Chris Paterson, Biju Das

Add QSPI0 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index a16a010..33661f8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -1357,6 +1357,30 @@ static const unsigned int mmc_ctrl_pins[] = {
 static const unsigned int mmc_ctrl_mux[] = {
 	MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
 };
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi0_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data2_pins[] = {
+	/* MOSI_IO0, MISO_IO1 */
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
+};
+static const unsigned int qspi0_data2_mux[] = {
+	QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
+};
+static const unsigned int qspi0_data4_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+	RCAR_GP_PIN(1, 20),
+};
+static const unsigned int qspi0_data4_mux[] = {
+	QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
+	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
+};
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_a_pins[] = {
 	/* RX, TX */
@@ -1628,6 +1652,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(mmc_data4),
 	SH_PFC_PIN_GROUP(mmc_data8),
 	SH_PFC_PIN_GROUP(mmc_ctrl),
+	SH_PFC_PIN_GROUP(qspi0_ctrl),
+	SH_PFC_PIN_GROUP(qspi0_data2),
+	SH_PFC_PIN_GROUP(qspi0_data4),
 	SH_PFC_PIN_GROUP(scif0_data_a),
 	SH_PFC_PIN_GROUP(scif0_data_b),
 	SH_PFC_PIN_GROUP(scif0_data_c),
@@ -1706,6 +1733,12 @@ static const char * const mmc_groups[] = {
 	"mmc_ctrl",
 };
 
+static const char * const qspi0_groups[] = {
+	"qspi0_ctrl",
+	"qspi0_data2",
+	"qspi0_data4",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data_a",
 	"scif0_data_b",
@@ -1765,6 +1798,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(du0),
 	SH_PFC_FUNCTION(i2c4),
 	SH_PFC_FUNCTION(mmc),
+	SH_PFC_FUNCTION(qspi0),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif2),
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  2018-09-18 13:47 [PATCH 0/5] Add I2C4/DU0/QSPI0/SDHI2/USB to r8a77470 Fabrizio Castro
                   ` (2 preceding siblings ...)
  2018-09-18 13:47 ` [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 " Fabrizio Castro
@ 2018-09-18 13:47 ` Fabrizio Castro
  2018-09-19  9:19   ` Geert Uytterhoeven
  2018-09-18 13:47 ` [PATCH 5/5] pinctrl: sh-pfc: r8a77470: Add USB " Fabrizio Castro
  4 siblings, 1 reply; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-18 13:47 UTC (permalink / raw)
  To: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij
  Cc: Fabrizio Castro, linux-renesas-soc, linux-gpio, Simon Horman,
	Chris Paterson, Biju Das

Add SDHI2 pin groups and functions to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 51 +++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index 33661f8..43ad702 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -1619,6 +1619,43 @@ static const unsigned int scif_clk_b_pins[] = {
 static const unsigned int scif_clk_b_mux[] = {
 	SCIF_CLK_B_MARK,
 };
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(4, 16),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+	SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+	/* D[0:3] */
+	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+	RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+	SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+	/* CLK, CMD */
+	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+	SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+	/* CD */
+	RCAR_GP_PIN(4, 20),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+	SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+	/* WP */
+	RCAR_GP_PIN(4, 21),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+	SD2_WP_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(avb_col),
@@ -1688,6 +1725,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scif5_data_f),
 	SH_PFC_PIN_GROUP(scif_clk_a),
 	SH_PFC_PIN_GROUP(scif_clk_b),
+	SH_PFC_PIN_GROUP(sdhi2_data1),
+	SH_PFC_PIN_GROUP(sdhi2_data4),
+	SH_PFC_PIN_GROUP(sdhi2_ctrl),
+	SH_PFC_PIN_GROUP(sdhi2_cd),
+	SH_PFC_PIN_GROUP(sdhi2_wp),
 };
 
 static const char * const avb_groups[] = {
@@ -1793,6 +1835,14 @@ static const char * const scif_clk_groups[] = {
 	"scif_clk_b",
 };
 
+static const char * const sdhi2_groups[] = {
+	"sdhi2_data1",
+	"sdhi2_data4",
+	"sdhi2_ctrl",
+	"sdhi2_cd",
+	"sdhi2_wp",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(avb),
 	SH_PFC_FUNCTION(du0),
@@ -1806,6 +1856,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif4),
 	SH_PFC_FUNCTION(scif5),
 	SH_PFC_FUNCTION(scif_clk),
+	SH_PFC_FUNCTION(sdhi2),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* [PATCH 5/5] pinctrl: sh-pfc: r8a77470: Add USB pin groups
  2018-09-18 13:47 [PATCH 0/5] Add I2C4/DU0/QSPI0/SDHI2/USB to r8a77470 Fabrizio Castro
                   ` (3 preceding siblings ...)
  2018-09-18 13:47 ` [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 " Fabrizio Castro
@ 2018-09-18 13:47 ` Fabrizio Castro
  2018-09-19  9:21   ` Geert Uytterhoeven
  4 siblings, 1 reply; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-18 13:47 UTC (permalink / raw)
  To: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij
  Cc: Fabrizio Castro, linux-renesas-soc, linux-gpio, Simon Horman,
	Chris Paterson, Biju Das

Add USB[01] pin groups and functions to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index 43ad702..3d36e5f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -1656,6 +1656,24 @@ static const unsigned int sdhi2_wp_pins[] = {
 static const unsigned int sdhi2_wp_mux[] = {
 	SD2_WP_MARK,
 };
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+	RCAR_GP_PIN(0, 0), /* PWEN */
+	RCAR_GP_PIN(0, 1), /* OVC */
+};
+static const unsigned int usb0_mux[] = {
+	USB0_PWEN_MARK,
+	USB0_OVC_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+	RCAR_GP_PIN(0, 2), /* PWEN */
+	RCAR_GP_PIN(0, 3), /* OVC */
+};
+static const unsigned int usb1_mux[] = {
+	USB1_PWEN_MARK,
+	USB1_OVC_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(avb_col),
@@ -1730,6 +1748,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
 	SH_PFC_PIN_GROUP(sdhi2_cd),
 	SH_PFC_PIN_GROUP(sdhi2_wp),
+	SH_PFC_PIN_GROUP(usb0),
+	SH_PFC_PIN_GROUP(usb1),
 };
 
 static const char * const avb_groups[] = {
@@ -1843,6 +1863,14 @@ static const char * const sdhi2_groups[] = {
 	"sdhi2_wp",
 };
 
+static const char * const usb0_groups[] = {
+	"usb0",
+};
+
+static const char * const usb1_groups[] = {
+	"usb1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(avb),
 	SH_PFC_FUNCTION(du0),
@@ -1857,6 +1885,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif5),
 	SH_PFC_FUNCTION(scif_clk),
 	SH_PFC_FUNCTION(sdhi2),
+	SH_PFC_FUNCTION(usb0),
+	SH_PFC_FUNCTION(usb1),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 20+ messages in thread

* Re: [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
  2018-09-18 13:47 ` [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups Fabrizio Castro
@ 2018-09-19  8:57   ` Geert Uytterhoeven
  2018-09-19  9:49     ` Fabrizio Castro
  0 siblings, 1 reply; 20+ messages in thread
From: Geert Uytterhoeven @ 2018-09-19  8:57 UTC (permalink / raw)
  To: Fabrizio Castro
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

Hi Fabrizio,

On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add I2C4 pin groups and function to the R8A77470 SoC.

Thanks for your patch!

Any specific reason you added I2C4 only, and not the other I2C instances?
Usually we add all of them in one run.

> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
  2018-09-18 13:47 ` [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 " Fabrizio Castro
@ 2018-09-19  9:07   ` Geert Uytterhoeven
  2018-09-19  9:53     ` Fabrizio Castro
  0 siblings, 1 reply; 20+ messages in thread
From: Geert Uytterhoeven @ 2018-09-19  9:07 UTC (permalink / raw)
  To: Fabrizio Castro
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

Hi Fabrizio,

On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add DU0 pin groups and function to the R8A77470 SoC.

Thanks for your patch!

Same question: no need for DU1?

> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
  2018-09-18 13:47 ` [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 " Fabrizio Castro
@ 2018-09-19  9:16   ` Geert Uytterhoeven
  2018-09-19  9:55     ` Fabrizio Castro
  0 siblings, 1 reply; 20+ messages in thread
From: Geert Uytterhoeven @ 2018-09-19  9:16 UTC (permalink / raw)
  To: Fabrizio Castro
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add QSPI0 pin groups and function to the R8A77470 SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

But I missed QSPI1...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  2018-09-18 13:47 ` [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 " Fabrizio Castro
@ 2018-09-19  9:19   ` Geert Uytterhoeven
  2018-09-19 10:19     ` Fabrizio Castro
  0 siblings, 1 reply; 20+ messages in thread
From: Geert Uytterhoeven @ 2018-09-19  9:19 UTC (permalink / raw)
  To: Fabrizio Castro
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add SDHI2 pin groups and functions to the R8A77470 SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

But there are more SDHI channels?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 5/5] pinctrl: sh-pfc: r8a77470: Add USB pin groups
  2018-09-18 13:47 ` [PATCH 5/5] pinctrl: sh-pfc: r8a77470: Add USB " Fabrizio Castro
@ 2018-09-19  9:21   ` Geert Uytterhoeven
  0 siblings, 0 replies; 20+ messages in thread
From: Geert Uytterhoeven @ 2018-09-19  9:21 UTC (permalink / raw)
  To: Fabrizio Castro
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Add USB[01] pin groups and functions to the R8A77470 SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
  2018-09-19  8:57   ` Geert Uytterhoeven
@ 2018-09-19  9:49     ` Fabrizio Castro
  2018-09-20 10:07       ` Geert Uytterhoeven
  0 siblings, 1 reply; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-19  9:49 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

Hello Geert,

Thank you for your feedback.

> Subject: Re: [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
>
> Hi Fabrizio,
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add I2C4 pin groups and function to the R8A77470 SoC.
>
> Thanks for your patch!
>
> Any specific reason you added I2C4 only, and not the other I2C instances?
> Usually we add all of them in one run.

The iwg23s is a very small Raspberry Pi like SBC, there isn't much on it, therefore we can't test all of the interfaces we would like to test.
The plan is to start supporting what we can easily test/access, for everything else we would like to wait and see, maybe at a later stage?

Thanks,
Fab

>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
  2018-09-19  9:07   ` Geert Uytterhoeven
@ 2018-09-19  9:53     ` Fabrizio Castro
  0 siblings, 0 replies; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-19  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

Hello Geert,

Thank you for your feedback.

> Subject: Re: [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
>
> Hi Fabrizio,
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add DU0 pin groups and function to the R8A77470 SoC.
>
> Thanks for your patch!
>
> Same question: no need for DU1?

There is no way we can test it on the iwg23s, therefore we have no plans for supporting DU1 at this point in time.

Thanks,
Fab

>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
  2018-09-19  9:16   ` Geert Uytterhoeven
@ 2018-09-19  9:55     ` Fabrizio Castro
  0 siblings, 0 replies; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-19  9:55 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

Hello Geert,

> Subject: Re: [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add QSPI0 pin groups and function to the R8A77470 SoC.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> But I missed QSPI1...

😃 same thing here, can't test QSPI1 easily, so for now we are going to leave this behind.

Thanks,
Fab

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  2018-09-19  9:19   ` Geert Uytterhoeven
@ 2018-09-19 10:19     ` Fabrizio Castro
  2018-09-20 10:04       ` Geert Uytterhoeven
  0 siblings, 1 reply; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-19 10:19 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

Hello Geert,

> Subject: Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
>
> On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add SDHI2 pin groups and functions to the R8A77470 SoC.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> But there are more SDHI channels?

We can't test SDHI0, and SDHI1 is used for the eMMC.

Although this patch is pretty much standard, I would like to start a discussion as while testing SDHI2 (which goes on the uSD connector on the bottom side of the iwg23s) I have come across an issue. The POC Control Register (IOCTRL6) of the RZ/G1C is structured in a completely different way from the other members of the RZ/G1 family, only one bit is used to control the interface, as opposed to the usual one bit per pin layout.

There are 3 possible ways to fix this:
1) keep the clk pin of the interface in a pin group on its own in the PFC driver (which means I would need to drop this patch or rework the pin groups with an additional patch), specify SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, keep the clk pin in a device tree node on its own in the board specific device tree and specify power-source only within the device tree node containing the clk line. The SD card device tree node in the board specific device tree would look like the following:
...
pinctrl-0 = <&sdhi2_pins>, <&sdhi2_pins_clk>;
pinctrl-1 = <&sdhi2_pins>, <&sdhi2_pins_clk_uhs>;
pinctrl-names = "default", "state_uhs";
....
2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to the interface, keep the SD card pin groups as specified by this patch, map all of the pins to the same bit in the POC register (as per pin_to_pocctrl is concerned), and the board specific device tree definitions would look like every other RZ/G1 or R-Car Gen2 boards that support SDR*
The only downside would be that the kernel would read-modify-write the POC Control Register with the same value for every line in the interface.

3) specify SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, come up with another macro for the other lines, keep the pin groups as specified by this patch, modify the logic of sh_pfc_pinconf_set and sh_pfc_pinconf_validate, and the board specific device tree would look like any other RZ/G1 or R-Car Gen2 board that supports SDR*

I am not particularly enthusiastic about option 3), but option 1) and option 2) seem equally sound to me.

What do you think about this?

Thanks,
Fab

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  2018-09-19 10:19     ` Fabrizio Castro
@ 2018-09-20 10:04       ` Geert Uytterhoeven
  2018-09-21 11:54         ` Fabrizio Castro
  2018-09-21 15:47         ` Wolfram Sang
  0 siblings, 2 replies; 20+ messages in thread
From: Geert Uytterhoeven @ 2018-09-20 10:04 UTC (permalink / raw)
  To: Fabrizio Castro
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das, Wolfram Sang

Hi Fabrizio,

CC wolfram

On Wed, Sep 19, 2018 at 12:19 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> Although this patch is pretty much standard, I would like to start a discussion as while testing SDHI2 (which goes on the uSD connector on the bottom side of the iwg23s) I have come across an issue. The POC Control Register (IOCTRL6) of the RZ/G1C is structured in a completely different way from the other members of the RZ/G1 family, only one bit is used to control the interface, as opposed to the usual one bit per pin layout.
>
> There are 3 possible ways to fix this:
> 1) keep the clk pin of the interface in a pin group on its own in the PFC driver (which means I would need to drop this patch or rework the pin groups with an additional patch), specify SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, keep the clk pin in a device tree node on its own in the board specific device tree and specify power-source only within the device tree node containing the clk line. The SD card device tree node in the board specific device tree would look like the following:
> ...
> pinctrl-0 = <&sdhi2_pins>, <&sdhi2_pins_clk>;
> pinctrl-1 = <&sdhi2_pins>, <&sdhi2_pins_clk_uhs>;
> pinctrl-names = "default", "state_uhs";
> ....

That matches the datasheet, which says the bit is for the CLK line,
but that can't
be true, as the voltage selection should affect other lines, too.

> 2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to the interface, keep the SD card pin groups as specified by this patch, map all of the pins to the same bit in the POC register (as per pin_to_pocctrl is concerned), and the board specific device tree definitions would look like every other RZ/G1 or R-Car Gen2 boards that support SDR*
> The only downside would be that the kernel would read-modify-write the POC Control Register with the same value for every line in the interface.

This looks the most sensible solution to me: just map in your
.pin_to_pocctrl() method
all pins of the interface to the single bit.

> 3) specify SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, come up with another macro for the other lines, keep the pin groups as specified by this patch, modify the logic of sh_pfc_pinconf_set and sh_pfc_pinconf_validate, and the board specific device tree would look like any other RZ/G1 or R-Car Gen2 board that supports SDR*

This looks overly complex.
So .pin_to_pocctrl() would need to return "ignore" for the other pins,
which can work easily for the "set" case, but not for the "get" case.

> I am not particularly enthusiastic about option 3), but option 1) and option 2) seem equally sound to me.
>
> What do you think about this?

I'd go for option 2.

Wolfram: what do you think?

Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
  2018-09-19  9:49     ` Fabrizio Castro
@ 2018-09-20 10:07       ` Geert Uytterhoeven
  0 siblings, 0 replies; 20+ messages in thread
From: Geert Uytterhoeven @ 2018-09-20 10:07 UTC (permalink / raw)
  To: Fabrizio Castro
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das

Hi Fabrizio,

On Wed, Sep 19, 2018 at 11:50 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> > Subject: Re: [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
> > On Tue, Sep 18, 2018 at 3:48 PM Fabrizio Castro
> > <fabrizio.castro@bp.renesas.com> wrote:
> > > Add I2C4 pin groups and function to the R8A77470 SoC.
> >
> > Thanks for your patch!
> >
> > Any specific reason you added I2C4 only, and not the other I2C instances?
> > Usually we add all of them in one run.
>
> The iwg23s is a very small Raspberry Pi like SBC, there isn't much on it, therefore we can't test all of the interfaces we would like to test.
> The plan is to start supporting what we can easily test/access, for everything else we would like to wait and see, maybe at a later stage?

If your target is just the iwg23s, this is indeed fine.
However, you may have customers who want to use this SoC in their own products,
and thus aren't limited to the pins available on iwg23s.
Including this support upstream makes their life easier. While not everything
can be tested, it will at least have received some review.

Anyway, I'll queue this series in sh-pfc-for-v4.20.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  2018-09-20 10:04       ` Geert Uytterhoeven
@ 2018-09-21 11:54         ` Fabrizio Castro
  2018-09-21 15:47         ` Wolfram Sang
  1 sibling, 0 replies; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-21 11:54 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das, Wolfram Sang

Hello Geert,

Thank you for your feedback!

> Subject: Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
>
> Hi Fabrizio,
>
> CC wolfram
>
> On Wed, Sep 19, 2018 at 12:19 PM Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Although this patch is pretty much standard, I would like to start a discussion as while testing SDHI2 (which goes on the uSD
> connector on the bottom side of the iwg23s) I have come across an issue. The POC Control Register (IOCTRL6) of the RZ/G1C is
> structured in a completely different way from the other members of the RZ/G1 family, only one bit is used to control the interface, as
> opposed to the usual one bit per pin layout.
> >
> > There are 3 possible ways to fix this:
> > 1) keep the clk pin of the interface in a pin group on its own in the PFC driver (which means I would need to drop this patch or
> rework the pin groups with an additional patch), specify SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, keep the clk pin in a
> device tree node on its own in the board specific device tree and specify power-source only within the device tree node containing
> the clk line. The SD card device tree node in the board specific device tree would look like the following:
> > ...
> > pinctrl-0 = <&sdhi2_pins>, <&sdhi2_pins_clk>;
> > pinctrl-1 = <&sdhi2_pins>, <&sdhi2_pins_clk_uhs>;
> > pinctrl-names = "default", "state_uhs";
> > ....
>
> That matches the datasheet, which says the bit is for the CLK line,
> but that can't
> be true, as the voltage selection should affect other lines, too.
>
> > 2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to the interface, keep the SD card pin groups as specified by
> this patch, map all of the pins to the same bit in the POC register (as per pin_to_pocctrl is concerned), and the board specific device
> tree definitions would look like every other RZ/G1 or R-Car Gen2 boards that support SDR*
> > The only downside would be that the kernel would read-modify-write the POC Control Register with the same value for every line in
> the interface.
>
> This looks the most sensible solution to me: just map in your
> .pin_to_pocctrl() method
> all pins of the interface to the single bit.
>
> > 3) specify SH_PFC_PIN_CFG_IO_VOLTAGE for the clock line alone, come up with another macro for the other lines, keep the pin
> groups as specified by this patch, modify the logic of sh_pfc_pinconf_set and sh_pfc_pinconf_validate, and the board specific device
> tree would look like any other RZ/G1 or R-Car Gen2 board that supports SDR*
>
> This looks overly complex.
> So .pin_to_pocctrl() would need to return "ignore" for the other pins,
> which can work easily for the "set" case, but not for the "get" case.
>
> > I am not particularly enthusiastic about option 3), but option 1) and option 2) seem equally sound to me.
> >
> > What do you think about this?
>
> I'd go for option 2.

Thank you for your advice, I am going to send a series implementing "option 2" shortly.

Thanks,
Fab

>
> Wolfram: what do you think?
>
> Thanks!
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  2018-09-20 10:04       ` Geert Uytterhoeven
  2018-09-21 11:54         ` Fabrizio Castro
@ 2018-09-21 15:47         ` Wolfram Sang
  2018-09-21 15:57           ` Fabrizio Castro
  1 sibling, 1 reply; 20+ messages in thread
From: Wolfram Sang @ 2018-09-21 15:47 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Fabrizio Castro, Laurent Pinchart, Geert Uytterhoeven,
	Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM,
	Simon Horman, Chris Paterson, Biju Das, Wolfram Sang

[-- Attachment #1: Type: text/plain, Size: 882 bytes --]


> > 2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to
> > the interface, keep the SD card pin groups as specified by this
> > patch, map all of the pins to the same bit in the POC register (as
> > per pin_to_pocctrl is concerned), and the board specific device tree
> > definitions would look like every other RZ/G1 or R-Car Gen2 boards
> > that support SDR* The only downside would be that the kernel would
> > read-modify-write the POC Control Register with the same value for
> > every line in the interface.

I don't think this multiple RMW is a problem.

> This looks the most sensible solution to me: just map in your
> .pin_to_pocctrl() method all pins of the interface to the single bit.

I didn't fully get if this one bit controls only the CLK wire or all the
relevant wires? I assume it is the latter one. For that, option 2) is
totally fine with me.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 20+ messages in thread

* RE: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
  2018-09-21 15:47         ` Wolfram Sang
@ 2018-09-21 15:57           ` Fabrizio Castro
  0 siblings, 0 replies; 20+ messages in thread
From: Fabrizio Castro @ 2018-09-21 15:57 UTC (permalink / raw)
  To: Wolfram Sang, Geert Uytterhoeven
  Cc: Laurent Pinchart, Geert Uytterhoeven, Linus Walleij,
	Linux-Renesas, open list:GPIO SUBSYSTEM, Simon Horman,
	Chris Paterson, Biju Das, Wolfram Sang

Hello Wolfram,

Thank you for your feedback!

> -----Original Message-----
> From: Wolfram Sang <wsa@the-dreams.de>
> Sent: 21 September 2018 16:48
> To: Geert Uytterhoeven <geert@linux-m68k.org>
> Cc: Fabrizio Castro <fabrizio.castro@bp.renesas.com>; Laurent Pinchart <laurent.pinchart@ideasonboard.com>; Geert Uytterhoeven
> <geert+renesas@glider.be>; Linus Walleij <linus.walleij@linaro.org>; Linux-Renesas <linux-renesas-soc@vger.kernel.org>; open
> list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>; Simon Horman <horms@verge.net.au>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Biju Das <biju.das@bp.renesas.com>; Wolfram Sang <wsa+renesas@sang-engineering.com>
> Subject: Re: [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
>
>
> > > 2) Specify SH_PFC_PIN_CFG_IO_VOLTAGE for every line that belongs to
> > > the interface, keep the SD card pin groups as specified by this
> > > patch, map all of the pins to the same bit in the POC register (as
> > > per pin_to_pocctrl is concerned), and the board specific device tree
> > > definitions would look like every other RZ/G1 or R-Car Gen2 boards
> > > that support SDR* The only downside would be that the kernel would
> > > read-modify-write the POC Control Register with the same value for
> > > every line in the interface.
>
> I don't think this multiple RMW is a problem.
>
> > This looks the most sensible solution to me: just map in your
> > .pin_to_pocctrl() method all pins of the interface to the single bit.
>
> I didn't fully get if this one bit controls only the CLK wire or all the
> relevant wires? I assume it is the latter one. For that, option 2) is
> totally fine with me.

It is not super clear what the intended behaviour is from the HW User's manual indeed,
but I have tested SDR50 and it seems to be working fine, which would indicate that the
control bit in the POC Control Register is actually controlling all of the lines of the
interface, and not just the CLK pin.

Thanks,
Fab



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, other threads:[~2018-09-21 21:47 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-18 13:47 [PATCH 0/5] Add I2C4/DU0/QSPI0/SDHI2/USB to r8a77470 Fabrizio Castro
2018-09-18 13:47 ` [PATCH 1/5] pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups Fabrizio Castro
2018-09-19  8:57   ` Geert Uytterhoeven
2018-09-19  9:49     ` Fabrizio Castro
2018-09-20 10:07       ` Geert Uytterhoeven
2018-09-18 13:47 ` [PATCH 2/5] pinctrl: sh-pfc: r8a77470: Add DU0 " Fabrizio Castro
2018-09-19  9:07   ` Geert Uytterhoeven
2018-09-19  9:53     ` Fabrizio Castro
2018-09-18 13:47 ` [PATCH 3/5] pinctrl: sh-pfc: r8a77470: Add QSPI0 " Fabrizio Castro
2018-09-19  9:16   ` Geert Uytterhoeven
2018-09-19  9:55     ` Fabrizio Castro
2018-09-18 13:47 ` [PATCH 4/5] pinctrl: sh-pfc: r8a77470: Add SDHI2 " Fabrizio Castro
2018-09-19  9:19   ` Geert Uytterhoeven
2018-09-19 10:19     ` Fabrizio Castro
2018-09-20 10:04       ` Geert Uytterhoeven
2018-09-21 11:54         ` Fabrizio Castro
2018-09-21 15:47         ` Wolfram Sang
2018-09-21 15:57           ` Fabrizio Castro
2018-09-18 13:47 ` [PATCH 5/5] pinctrl: sh-pfc: r8a77470: Add USB " Fabrizio Castro
2018-09-19  9:21   ` Geert Uytterhoeven

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