From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [4/5] dmaengine: sprd: Add Spreadtrum DMA configuration From: Baolin Wang Message-Id: Date: Fri, 13 Apr 2018 13:44:04 +0800 To: Vinod Koul Cc: Dan Williams , Eric Long , Mark Brown , dmaengine@vger.kernel.org, LKML List-ID: T24gMTMgQXByaWwgMjAxOCBhdCAxMTozOSwgVmlub2QgS291bCA8dmlub2Qua291bEBpbnRlbC5j b20+IHdyb3RlOgo+IE9uIFRodSwgQXByIDEyLCAyMDE4IGF0IDA3OjMwOjAxUE0gKzA4MDAsIEJh b2xpbiBXYW5nIHdyb3RlOgo+Cj4+ID4+ID4gd2hhdCBkb2VzIGJsb2NrIGFuZCB0cmFuc2FjdGlv biBsZW4gcmVmZXIgdG8gaGVyZQo+PiA+Pgo+PiA+PiAgT3VyIERNQSBoYXMgMyB0cmFuc2ZlciBt b2RlOiB0cmFuc2FjdGlvbiB0cmFuc2ZlciwgYmxvY2sgdHJhbnNmZXIgYW5kCj4+ID4+IGZyYWdt ZW50IHRyYW5zZmVyLiBPbmUgdHJhbnNhY3Rpb24gdHJhbnNmZXIgY2FuIGNvbnRhaW4gc2V2ZXJh bCBibG9ja3MKPj4gPj4gdHJhbnNmZXIsIGFuZCBlYWNoIGJsb2NrIGNhbiBiZSBzZXQgcHJvcGVy IGJsb2NrIHN0ZXAuIE9uZSBibG9jayBjYW4KPj4gPj4gY29udGFpbiBzZXZlcmFsIGZyYWdtZW50 cyB0cmFuc2ZlciB3aXRoIHByb3BlciBmcmFnbWVudCBzdGVwLiBJdCBjYW4KPj4gPj4gZ2VuZXJh dGUgaW50ZXJydXB0cyB3aGVuIG9uZSB0cmFuc2FjdGlvbiB0cmFuc2ZlciBvciBibG9jayB0cmFu c2ZlciBvcgo+PiA+PiBmcmFnbWVudCB0cmFuc2ZlciBpcyBjb21wbGV0ZWQgaWYgdXNlciBzZXQg dGhlIGludGVycnVwdCB0eXBlLiBTbyBoZXJlCj4+ID4+IHdlIHNob3VsZCBzZXQgdGhlIGxlbmd0 aCBmb3IgdHJhbnNhY3Rpb24gdHJhbnNmZXIsIGJsb2NrIHRyYW5zZmVyIGFuZAo+PiA+PiBmcmFn bWVudCB0cmFuc2Zlci4KPj4gPgo+PiA+IHdoYXQgYXJlIHRoZSBtYXggc2l6ZSB0aGVzZSB0eXBl cyBzdXBwb3J0Pwo+Pgo+PiBUaGVzZSB0eXBlcyBtYXggc2l6ZSBkZWZpbml0aW9uOgo+Pgo+PiAj ZGVmaW5lIFNQUkRfRE1BX0ZSR19MRU5fTUFTSyBHRU5NQVNLKDE2LCAwKQo+Pgo+PiAjZGVmaW5l IFNQUkRfRE1BX0JMS19MRU5fTUFTSyBHRU5NQVNLKDE2LCAwKQo+Pgo+PiAjZGVmaW5lIFNQUkRf RE1BX1RSU0NfTEVOX01BU0sgR0VOTUFTSygyNywgMCkKPgo+IFRoZXkgYXJlIHJlZ2lzdGVyIGRl ZmluZXMuIEhvdyBtYW55IGl0ZW1zIG9yIGJ5dGVzIGRvIGVhY2ggdHlwZSBvZiB0eG4KPiBzdXBw b3J0PwoKVGhlc2UgbWFjcm9zIGFyZSB0aGUgbWF4IHNpemUgZGVmaW5pdGlvbnMsIGZvciBleGFt cGxlIG9uZSBmcmFnbWVudApsZW5ndGggY2FuIHN1cHBvcnQgdG8gMHgxZmZmZiBieXRlcywgb25l IHRyYW5zYWN0aW9uIHRyYW5zZmVyIGNhbgpzdXBwb3J0IHRvIDB4ZmZmZmZmZi4K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751148AbeDMFoH (ORCPT ); Fri, 13 Apr 2018 01:44:07 -0400 Received: from mail-ot0-f170.google.com ([74.125.82.170]:41611 "EHLO mail-ot0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750849AbeDMFoF (ORCPT ); Fri, 13 Apr 2018 01:44:05 -0400 X-Google-Smtp-Source: AIpwx482w3g+wPckNDUXahZ5cjKrnQfWJ+fsN/cT2wfELHNIwZpuJ5zr5LglmphKq/Jtowoo0ts/aP4lbg9PhFvtQ2w= MIME-Version: 1.0 In-Reply-To: <20180413033917.GH6014@localhost> References: <0c2b76aba6a49e583f920ae582d6815fa9cc4361.1523346135.git.baolin.wang@linaro.org> <20180411093634.GC6014@localhost> <20180412093735.GF6014@localhost> <20180413033917.GH6014@localhost> From: Baolin Wang Date: Fri, 13 Apr 2018 13:44:04 +0800 Message-ID: Subject: Re: [PATCH 4/5] dmaengine: sprd: Add Spreadtrum DMA configuration To: Vinod Koul Cc: Dan Williams , Eric Long , Mark Brown , dmaengine@vger.kernel.org, LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13 April 2018 at 11:39, Vinod Koul wrote: > On Thu, Apr 12, 2018 at 07:30:01PM +0800, Baolin Wang wrote: > >> >> > what does block and transaction len refer to here >> >> >> >> Our DMA has 3 transfer mode: transaction transfer, block transfer and >> >> fragment transfer. One transaction transfer can contain several blocks >> >> transfer, and each block can be set proper block step. One block can >> >> contain several fragments transfer with proper fragment step. It can >> >> generate interrupts when one transaction transfer or block transfer or >> >> fragment transfer is completed if user set the interrupt type. So here >> >> we should set the length for transaction transfer, block transfer and >> >> fragment transfer. >> > >> > what are the max size these types support? >> >> These types max size definition: >> >> #define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0) >> >> #define SPRD_DMA_BLK_LEN_MASK GENMASK(16, 0) >> >> #define SPRD_DMA_TRSC_LEN_MASK GENMASK(27, 0) > > They are register defines. How many items or bytes do each type of txn > support? These macros are the max size definitions, for example one fragment length can support to 0x1ffff bytes, one transaction transfer can support to 0xfffffff. -- Baolin.wang Best Regards