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From: Brian Gerst <brgerst@gmail.com>
Date: Fri, 5 Jan 2018 11:35:24 -0500
Message-ID: <CAMzpN2hi9QkamCX2QvS8ukwJQtGKShLs6V2RmM8VjXF+8PdDxQ@mail.gmail.com>
Subject: Re: [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: "the arch/x86 maintainers" <x86@kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Dave Hansen <dave.hansen@intel.com>,
        Borislav Petkov <bp@alien8.de>,
        Thomas Gleixner <tglx@linutronix.de>,
        Tim Chen <tim.c.chen@linux.intel.com>,
        Greg Kroah-Hartman <gregkh@linux-foundation.org>,
        David Woodhouse <dwmw@amazon.co.uk>,
        Paul Turner <pjt@google.com>
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On Fri, Jan 5, 2018 at 11:07 AM, Tom Lendacky <thomas.lendacky@amd.com> wrote:
> To aid in speculation control, make LFENCE a serializing instruction.
> This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
> that support LFENCE do not have this MSR.  For these families, the LFENCE
> instruction is already serializing.

Does this require a microcode update?

--
Brian Gerst