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Date: Tue, 31 Mar 2015 18:21:42 -0400
Message-ID: <CAMzpN2iWm5r-n21yEJo11eNPhkFqcLo7OnPqGunJoRfKEkEhtg@mail.gmail.com>
Subject: Re: [PATCH 7/9] x86/asm/entry/32: tidy up some instructions
From: Brian Gerst <brgerst@gmail.com>
To: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Ingo Molnar <mingo@kernel.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Steven Rostedt <rostedt@goodmis.org>, Borislav Petkov <bp@alien8.de>,
        "H. Peter Anvin" <hpa@zytor.com>,
        Andy Lutomirski <luto@amacapital.net>, Oleg Nesterov <oleg@redhat.com>,
        Frederic Weisbecker <fweisbec@gmail.com>,
        Alexei Starovoitov <ast@plumgrid.com>, Will Drewry <wad@chromium.org>,
        Kees Cook <keescook@chromium.org>,
        "the arch/x86 maintainers" <x86@kernel.org>,
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On Tue, Mar 31, 2015 at 1:00 PM, Denys Vlasenko <dvlasenk@redhat.com> wrote:
> After TESTs, use logically correct JZ mnemonic instead of JE
> (this doesn't change code).
>
> Tidy up CMPW insns:
>
> Modern CPUs are not good with 16-bit operations.
> The instructions with 16-bit immediates are especially bad,
> on many CPUs they cause length changing prefix stall
> in the decoders, costing ~6 cycles to recover.
>
> Replace CMPWs with CMPLs.
> Of these, for form with 8-bit sign-extended immediates
> it is a win because they are smaller now
> (no 0x66 prefix anymore);
> ones with 16-bit immediates are faster.
>
> @@ -708,7 +708,7 @@ END(sysenter_badsys)
>  #ifdef CONFIG_X86_ESPFIX32
>         movl %ss, %eax
>         /* see if on espfix stack */
> -       cmpw $__ESPFIX_SS, %ax
> +       cmpl $__ESPFIX_SS, %eax
>         jne 27f
>         movl $__KERNEL_DS, %eax
>         movl %eax, %ds

This is incorrect.  32-bit reads from a segment register are not
zero-extended.  The upper 16 bits are implementation-defined.  Most
processors will clear them but it's not guaranteed.

--
Brian Gerst