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Tue, 15 Jun 2021 05:08:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rickchen36@gmail.com Received: by mail-il1-x12d.google.com with SMTP id b14so14058027ilq.7 for ; Mon, 14 Jun 2021 20:08:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=kT+hbS0QO9oW4rWxiw7X2xO16BYg/WHlgnnYewwI5FU=; b=oKfjZnljqaEmzJ3pOcCux/htIr7NSqVKU8lGThnSYktQd7/euA1KXqz4elRwnahrbf V/LpLA4UtpdTgNY4mKaXg1H6EKux2H4EAxtUXM6gO8BZ6wG4LfkqKDO8twaKiiNYonrd oPnh2EQ7KEd/IdIS8CNzgxJQneD1HJijaU3CZ7U0Xes4P4Bhi1cNaYVXJ+Tx7K9COwFC ddCV/J+rjrrISpHnnBFgaTzk9lxqKyqM3OoFe7PRzauazqSClux3krjzLAoh1j1H17jq MGfQ1u3XG+/fu4dkMUsexSvq7U2c4V/i7udfnvU6btKWhAJXhBx6oEf5LgY1B1v6eqKi SQ+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=kT+hbS0QO9oW4rWxiw7X2xO16BYg/WHlgnnYewwI5FU=; b=QPCmhDGJV914p7Ch9oqj++PH82s3N+Vd0ZZEr7HZGJnwjST6SkXlCHXLqlExHnA4qr EXgFNW17sOHhuM249EOoSPjPEkFdL+Xl0/bIa2zBMQhJVVMb/i4DnogYyEjFMU+5paqs fGEAF2SzutffBxUVkL271PRj1Q+KLH1dRMJFvYl/kPhOeN5DJmZblYtTcITy7BVSlJio n7jakJTZJ7gA2sHNfV/8hphovZREQxYkx3ZY6ZAbCobCal2/azV/TCRpccQTb87uQg7N 8h9ZlxX0BiVuY3wytHNp7XAg/lneoM6C+1Bh4erAARIM3h6aRd7iCWh6vYtqW0h20j09 bRAg== X-Gm-Message-State: AOAM530QzlKnujGwWEgxFY2gL1MY184nAQMrd599R8PneKCLTqH/ocEJ nf+2Q5Jn0qwz11uAfyCEWjS80qmPkAE99juu7Ts= X-Google-Smtp-Source: ABdhPJyoDxtdaZsPxAbI5pNARWxs9Svk1hSY8d1R7Pvf9Dy4cSvYkSQkK+/iS+7uVCGLohWpxR3k/AhTwSMtQ67zuck= X-Received: by 2002:a05:6e02:12ef:: with SMTP id l15mr16430054iln.153.1623726508671; Mon, 14 Jun 2021 20:08:28 -0700 (PDT) MIME-Version: 1.0 References: <20210609075602.157709-1-bmeng.cn@gmail.com> <752D002CFF5D0F4FA35C0100F1D73F3FE5EA99D2@ATCPCS12.andestech.com> In-Reply-To: <752D002CFF5D0F4FA35C0100F1D73F3FE5EA99D2@ATCPCS12.andestech.com> From: Rick Chen Date: Tue, 15 Jun 2021 11:08:17 +0800 Message-ID: Subject: Re: [RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask To: Bin Meng Cc: U-Boot Mailing List , Leo Liang , rick Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Bin > From: Bin Meng > Sent: Monday, June 14, 2021 11:48 AM > To: Rick Jian-Zhi Chen(=E9=99=B3=E5=BB=BA=E5=BF=97) ;= Leo Yu-Chi Liang(=E6=A2=81=E8=82=B2=E9=BD=8A) ; U-B= oot Mailing List > Subject: Re: [RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask > > On Wed, Jun 9, 2021 at 3:55 PM Bin Meng wrote: > > > > Current logic in riscv_get_ipi() for Andes PLICSW does not look good > > to me. The mask to test IPI pending bits for a hart should be left > > shifted by (8 * gd->arch.boot_hart), just the same as what is done in > > riscv_send_ipi(). > > > > Signed-off-by: Bin Meng > > > > --- > > It looks there is no datasheet released from Andes that describes how > > PLICSW works, and its register fields. I can only get an understanding > > from current U-Boot and OpenSBI PLICSW driver. > > > > This requires testing on Andes hardware, which I don't have access to. > > > > arch/riscv/lib/andes_plic.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > Ping? Though there will be only one hart will jump to U-Boot proper currently, and this delay loop seem to be unnecessary. But it is still a good catch. Thanks, Rick Tested-by: Rick Chen Reviewed-by: Rick Chen