From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rick Chen Date: Thu, 26 Nov 2020 17:13:41 +0800 Subject: [PATCH] riscv: timer: Add support for an early timer In-Reply-To: References: <20201117110508.25819-1-pragnesh.patel@sifive.com> <752D002CFF5D0F4FA35C0100F1D73F3FB23051F0@ATCPCS16.andestech.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Pragnesh > Hi Rick, > > >-----Original Message----- > >From: Rick Chen > >Sent: 24 November 2020 13:08 > >To: Pragnesh Patel > >Cc: U-Boot Mailing List ; Atish Patra > >; Bin Meng ; Paul Walmsley ( > >Sifive) ; Anup Patel ; Sagar > >Kadam ; Palmer Dabbelt ; > >Simon Glass ; rick ; Alan Kao > >; Leo Liang > >Subject: Re: [PATCH] riscv: timer: Add support for an early timer > > > >[External Email] Do not click links or attachments unless you recognize the > >sender and know the content is safe > > > >Hi Pragnesh, > > > >> From: Pragnesh Patel [mailto:pragnesh.patel at sifive.com] > >> Sent: Tuesday, November 17, 2020 7:05 PM > >> To: u-boot at lists.denx.de > >> Cc: atish.patra at wdc.com; palmerdabbelt at google.com; > >bmeng.cn at gmail.com; > >> paul.walmsley at sifive.com; anup.patel at wdc.com; sagar.kadam at sifive.com; > >> Rick Jian-Zhi Chen(???); Pragnesh Patel; Palmer Dabbelt; Sean > >> Anderson; Simon Glass; Bin Meng > >> Subject: [PATCH] riscv: timer: Add support for an early timer > >> > >> Added support for timer_early_get_count() and timer_early_get_rate() > >> This is mostly useful in tracing. > >> > >> Signed-off-by: Pragnesh Patel > >> --- > >> drivers/timer/andes_plmt_timer.c | 21 ++++++++++++++++++++- > >> drivers/timer/riscv_timer.c | 21 ++++++++++++++++++++- > >> drivers/timer/sifive_clint_timer.c | 21 ++++++++++++++++++++- > >> include/configs/ax25-ae350.h | 5 +++++ > >> include/configs/sifive-fu540.h | 5 +++++ > >> 5 files changed, 70 insertions(+), 3 deletions(-) > >> > > > >I verify with ae350_rv64_defconfig > > > >make FTRACE=1 ae350_rv64_defconfig > >make FTRACE=1 > > > >and it boot fail as below: > > > >U-Boot 2021.01-rc2-00140-geb42715 (Nov 24 2020 - 15:02:18 +0800) > > > >DRAM: 1 GiB > >trace: enabled > > > >DO you have any suggestions ? > > Please enable CONFIG_TIMER_EARLY=y in ae350_rv64_defconfig > > Actually in v2, I will make TRACE to select TIMER_EARLY like below, > > --- a/lib/Kconfig > +++ b/lib/Kconfig > @@ -210,6 +210,7 @@ config BITREVERSE > config TRACE > bool "Support for tracing of function calls and timing" > imply CMD_TRACE > + select TIMER_EARLY > > Let me know if you have any suggestion. OK. After add CONFIG_TIMER_EARLY, U-Boot boots ok. But When I try to booting kernel with FTRACE=1, following are the test stats: ae350_rv64_spl_defconfig without FTRACE=1, kernel booting is ok. ae350_rv64_spl_defconfig with FTRACE=1, kernel booting fail. ae350_rv64_defconfig with FTRACE=1, kernel booting is ok The failure case seems not reasonable. Any suggestions ? Thanks, Rick > > > > >Thanks, > >Rick > > > >> diff --git a/drivers/timer/andes_plmt_timer.c > >> b/drivers/timer/andes_plmt_timer.c > >> index cec86718c7..74b795c97a 100644 > >> --- a/drivers/timer/andes_plmt_timer.c > >> +++ b/drivers/timer/andes_plmt_timer.c > >> @@ -17,11 +17,30 @@ > >> /* mtime register */ > >> #define MTIME_REG(base) ((ulong)(base)) > >> > >> -static u64 andes_plmt_get_count(struct udevice *dev) > >> +static u64 notrace andes_plmt_get_count(struct udevice *dev) > >> { > >> return readq((void __iomem *)MTIME_REG(dev->priv)); } > >> > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE) > >> +/** > >> + * timer_early_get_rate() - Get the timer rate before driver model > >> +*/ unsigned long notrace timer_early_get_rate(void) { > >> + return RISCV_MMODE_TIMER_FREQ; } > >> + > >> +/** > >> + * timer_early_get_count() - Get the timer count before driver model > >> + * > >> + */ > >> +u64 notrace timer_early_get_count(void) { > >> + return readq((void __iomem > >> +*)MTIME_REG(RISCV_MMODE_TIMERBASE)); > >> +} > >> +#endif > >> + > >> static const struct timer_ops andes_plmt_ops = { > >> .get_count = andes_plmt_get_count, }; diff --git > >> a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index > >> 21ae184057..a0f71ca897 100644 > >> --- a/drivers/timer/riscv_timer.c > >> +++ b/drivers/timer/riscv_timer.c > >> @@ -16,7 +16,7 @@ > >> #include > >> #include > >> > >> -static u64 riscv_timer_get_count(struct udevice *dev) > >> +static u64 notrace riscv_timer_get_count(struct udevice *dev) > >> { > >> __maybe_unused u32 hi, lo; > >> > >> @@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev) > >> return ((u64)hi << 32) | lo; > >> } > >> > >> +#if CONFIG_IS_ENABLED(RISCV_SMODE) > >> +/** > >> + * timer_early_get_rate() - Get the timer rate before driver model > >> +*/ unsigned long notrace timer_early_get_rate(void) { > >> + return RISCV_SMODE_TIMER_FREQ; } > >> + > >> +/** > >> + * timer_early_get_count() - Get the timer count before driver model > >> + * > >> + */ > >> +u64 notrace timer_early_get_count(void) { > >> + return riscv_timer_get_count(NULL); } #endif > >> + > >> static int riscv_timer_probe(struct udevice *dev) { > >> struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); > >> diff --git a/drivers/timer/sifive_clint_timer.c > >> b/drivers/timer/sifive_clint_timer.c > >> index 00ce0f08d6..9ae05a0e7e 100644 > >> --- a/drivers/timer/sifive_clint_timer.c > >> +++ b/drivers/timer/sifive_clint_timer.c > >> @@ -14,11 +14,30 @@ > >> /* mtime register */ > >> #define MTIME_REG(base) ((ulong)(base) + 0xbff8) > >> > >> -static u64 sifive_clint_get_count(struct udevice *dev) > >> +static u64 notrace sifive_clint_get_count(struct udevice *dev) > >> { > >> return readq((void __iomem *)MTIME_REG(dev->priv)); } > >> > >> +#if CONFIG_IS_ENABLED(RISCV_MMODE) > >> +/** > >> + * timer_early_get_rate() - Get the timer rate before driver model > >> +*/ unsigned long notrace timer_early_get_rate(void) { > >> + return RISCV_MMODE_TIMER_FREQ; } > >> + > >> +/** > >> + * timer_early_get_count() - Get the timer count before driver model > >> + * > >> + */ > >> +u64 notrace timer_early_get_count(void) { > >> + return readq((void __iomem > >> +*)MTIME_REG(RISCV_MMODE_TIMERBASE)); > >> +} > >> +#endif > >> + > >> static const struct timer_ops sifive_clint_ops = { > >> .get_count = sifive_clint_get_count, }; diff --git > >> a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index > >> b2606e794d..bd9c371f83 100644 > >> --- a/include/configs/ax25-ae350.h > >> +++ b/include/configs/ax25-ae350.h > >> @@ -17,6 +17,11 @@ > >> #endif > >> #endif > >> > >> +#define RISCV_MMODE_TIMERBASE 0xe6000000 > >> +#define RISCV_MMODE_TIMER_FREQ 60000000 > >> + > >> +#define RISCV_SMODE_TIMER_FREQ 60000000 > >> + > >> /* > >> * CPU and Board Configuration Options > >> */ > >> diff --git a/include/configs/sifive-fu540.h > >> b/include/configs/sifive-fu540.h index c1c79db147..0d69d1c548 100644 > >> --- a/include/configs/sifive-fu540.h > >> +++ b/include/configs/sifive-fu540.h > >> @@ -36,6 +36,11 @@ > >> > >> #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 > >> > >> +#define RISCV_MMODE_TIMERBASE 0x2000000 > >> +#define RISCV_MMODE_TIMER_FREQ 1000000 > >> + > >> +#define RISCV_SMODE_TIMER_FREQ 1000000 > >> + > >> /* Environment options */ > >> > >> #ifndef CONFIG_SPL_BUILD > >> -- > >> 2.17.1