From mboxrd@z Thu Jan  1 00:00:00 1970
From: Rick Chen <rickchen36@gmail.com>
Date: Mon, 29 Apr 2019 11:00:49 +0800
Subject: [U-Boot] [PATCH v2 3/4] riscv: prior_stage_fdt_address should
 only be used when OF_PRIOR_STAGE is enabled
In-Reply-To: <8bdff540caa80bbd4ecea6b58bf9fde99b34ebcb.camel@aisec.fraunhofer.de>
References: <20190424063313.12188-1-uboot@andestech.com>
 <20190424063313.12188-4-uboot@andestech.com>
 <CAEUhbmVD5jjOH6s6Tf6BAeLCFX27bAB-iPHEeAWwCUYGq=hJxw@mail.gmail.com>
 <CAN5B=eLMX+Ww9bjz=WQJKT0FQXv_43-RwRdHe1ERBpEwA_m8JQ@mail.gmail.com>
 <8bdff540caa80bbd4ecea6b58bf9fde99b34ebcb.camel@aisec.fraunhofer.de>
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Auer, Lukas <lukas.auer@aisec.fraunhofer.de> 於 2019年4月26日 週五 上午4:58寫道：
>
> On Thu, 2019-04-25 at 09:00 +0800, Rick Chen wrote:
> > Bin Meng <bmeng.cn@gmail.com> 於 2019年4月24日 週三 下午3:02寫道：
> > > On Wed, Apr 24, 2019 at 2:38 PM Andes <uboot@andestech.com> wrote:
> > > > From: Rick Chen <rick@andestech.com>
> > > >
> > > > This patch will fix prior_stage_fdt_address write failure problem, when
> > > > AE350 was booting from flash.
> > >
> > > was -> is
> >
> > OK
> >
> > > > When AE350 was booting from falsh, prior_stage_fdt_address will be in
> > >
> > > was -> is
> >
> > OK
> >
> > > > flash address, we shall avoid it to be written.
> > > >
> > > > Signed-off-by: Rick Chen <rick@andestech.com>
> > > > Cc: Greentime Hu <greentime@andestech.com>
> > > > ---
> > > >  arch/riscv/cpu/cpu.c   | 2 ++
> > > >  arch/riscv/cpu/start.S | 2 ++
> > > >  2 files changed, 4 insertions(+)
> > > >
> > > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> > > > index 768c44c..a17d37f 100644
> > > > --- a/arch/riscv/cpu/cpu.c
> > > > +++ b/arch/riscv/cpu/cpu.c
> > > > @@ -15,7 +15,9 @@
> > > >   * The variables here must be stored in the data section since they are used
> > > >   * before the bss section is available.
> > > >   */
> > > > +#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
> > >
> > > Should this be: ifdef CONFIG_OF_PRIOR_STAGE, because the next a few of
> > > lines you wrote: #ifndef CONFIG_XIP
> >
> > I just refer to fdtdesc.c and imitate it.
> > But it is no problem to modify it as ifdef CONFIG_OF_PRIOR_STAGE as you said.
> >
>
> It might also makes sense to use #if CONFIG_IS_ENABLED() for both
> CONFIG_OF_PRIOR_STAGE and CONFIG_XIP. This way, once we support SPL for
> RISC-V, we won't have to make any additional changes.
> With SPL support, SPL would likely enable XIP while U-Boot proper would
> not (SPL running from flash and U-Boot proper from RAM). To support
> this we would have to use CONFIG_IS_ENABLED.
>
> If you choose to keep CONFIG_IS_ENABLED, please remove the spaces
> between # and if.
>

Thanks for explanation.
I will use #ifdef CONFIG_OF_PRIOR_STAGE

Thanks
Rick

> Thanks,
> Lukas
>
> > > >  phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
> > > > +#endif
> > > >  #ifndef CONFIG_XIP
> > > >  u32 hart_lottery __attribute__((section(".data"))) = 0;
> > > >  /*
> > > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
> > > > index 41d9a32..9ede1a7 100644
> > > > --- a/arch/riscv/cpu/start.S
> > > > +++ b/arch/riscv/cpu/start.S
> > > > @@ -111,7 +111,9 @@ call_board_init_f_0:
> > > >         bnez    tp, secondary_hart_loop
> > > >  #endif
> > > >
> > > > +#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
> > >
> > > #ifdef CONFIG_OF_PRIOR_STAGE ?
> >
> > OK
> >
> > > >         la      t0, prior_stage_fdt_address
> > > > +#endif
> > > >         SREG    s1, 0(t0)
> > > >
> > > >         jal     board_init_f_init_reserve
> > > > --
> > >
> > > Regards,
> > > Bin