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S." Date: Tue, 23 Mar 2021 08:12:06 +0530 Message-ID: Subject: Re: [PATCH 07/11] hw/gpio/avr_gpio: Add tracing for reads and writes To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="00000000000051f55805be2b223f" Received-SPF: pass client-ip=2607:f8b0:4864:20::d32; envelope-from=niteesh.gs@gmail.com; helo=mail-io1-xd32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000051f55805be2b223f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hii Phil, A gentle reminder to push these patches. Thanks, Niteesh. On Sat, Mar 13, 2021 at 10:51 PM Niteesh G. S. wrote= : > Reviewed-by: Niteesh G S > > On Sat, Mar 13, 2021 at 10:25 PM Philippe Mathieu-Daud=C3=A9 > wrote: > >> From: G S Niteesh Babu >> >> Added tracing for gpio read, write, and update output irq. >> >> 1) trace_avr_gpio_update_ouput_irq >> 2) trace_avr_gpio_read >> 3) trace_avr_gpio_write >> >> Signed-off-by: G S Niteesh Babu >> Reviewed-by: Michael Rolnik >> Message-Id: <20210311135539.10206-3-niteesh.gs@gmail.com> >> [PMD: Added port_name(), display port name in trace events] >> Signed-off-by: Philippe Mathieu-Daud=C3=A9 >> --- >> hw/gpio/avr_gpio.c | 26 +++++++++++++++++++++----- >> hw/gpio/trace-events | 5 +++++ >> 2 files changed, 26 insertions(+), 5 deletions(-) >> >> diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c >> index e4c7122e62c..29252d6ccfe 100644 >> --- a/hw/gpio/avr_gpio.c >> +++ b/hw/gpio/avr_gpio.c >> @@ -2,6 +2,7 @@ >> * AVR processors GPIO registers emulation. >> * >> * Copyright (C) 2020 Heecheol Yang >> + * Copyright (C) 2021 Niteesh Babu G S >> * >> * This program is free software; you can redistribute it and/or >> * modify it under the terms of the GNU General Public License as >> @@ -26,6 +27,12 @@ >> #include "hw/gpio/avr_gpio.h" >> #include "hw/qdev-properties.h" >> #include "migration/vmstate.h" >> +#include "trace.h" >> + >> +static char port_name(AVRGPIOState *s) >> +{ >> + return 'A' + s->id; >> +} >> >> static void avr_gpio_reset(DeviceState *dev) >> { >> @@ -47,32 +54,41 @@ static void avr_gpio_write_port(AVRGPIOState *s, >> uint64_t value) >> >> if (cur_ddr_pin_val && (cur_port_pin_val !=3D new_port_pin_val)= ) { >> qemu_set_irq(s->out[pin], new_port_pin_val); >> + trace_avr_gpio_update_output_irq(port_name(s), pin, >> new_port_pin_val); >> } >> } >> s->reg.port =3D value & s->reg.ddr; >> } >> static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int >> size) >> { >> + uint8_t val =3D 0; >> AVRGPIOState *s =3D (AVRGPIOState *)opaque; >> switch (offset) { >> case GPIO_PIN: >> - return s->reg.pin; >> + val =3D s->reg.pin; >> + break; >> case GPIO_DDR: >> - return s->reg.ddr; >> + val =3D s->reg.ddr; >> + break; >> case GPIO_PORT: >> - return s->reg.port; >> + val =3D s->reg.port; >> + break; >> default: >> g_assert_not_reached(); >> break; >> } >> - return 0; >> + >> + trace_avr_gpio_read(port_name(s), offset, val); >> + return val; >> } >> >> static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value, >> unsigned int size) >> { >> AVRGPIOState *s =3D (AVRGPIOState *)opaque; >> - value =3D value & 0xF; >> + value =3D value & 0xFF; >> + >> + trace_avr_gpio_write(port_name(s), offset, value); >> switch (offset) { >> case GPIO_PIN: >> s->reg.pin =3D value; >> diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events >> index 46ab9323bd0..640834597a8 100644 >> --- a/hw/gpio/trace-events >> +++ b/hw/gpio/trace-events >> @@ -18,3 +18,8 @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset >> 0x%" PRIx64 " value 0x%" P >> sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 = " >> value 0x%" PRIx64 >> sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" >> PRIi64 >> sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" >> PRIi64 " value %" PRIi64 >> + >> +# avr_gpio.c >> +avr_gpio_read(unsigned id, uint64_t offset, uint64_t r) "port %c offset >> 0x%" PRIx64 " value 0x%" PRIx64 >> +avr_gpio_write(unsigned id, uint64_t offset, uint64_t value) "port %c >> offset 0x%" PRIx64 " value 0x%" PRIx64 >> +avr_gpio_update_output_irq(unsigned id, int64_t line, int64_t value) >> "port %c pin %" PRIi64 " value %" PRIi64 >> -- >> 2.26.2 >> >> --00000000000051f55805be2b223f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hii= Phil,

A gentle reminder = to push these patches.

Th= anks,
Niteesh.<= /div>

On Sat, Mar 13, 2021 at 10:51 PM Niteesh G. S. <niteesh.gs@gmail.com> wrote:
Reviewed-by: Niteesh G S <niteesh.gs@gmail.com= >

On Sat, Mar 13, 2021 at 10:25 PM Philippe Mathieu-Daud=C3= =A9 <f4bug@amsat.or= g> wrote:
From: G S Niteesh Babu <niteesh.gs@gmail.com>

Added tracing for gpio read, write, and update output irq.

1) trace_avr_gpio_update_ouput_irq
2) trace_avr_gpio_read
3) trace_avr_gpio_write

Signed-off-by: G S Niteesh Babu <niteesh.gs@gmail.com>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Message-Id: <20210311135539.10206-3-niteesh.gs@gmail.com> [PMD: Added port_name(), display port name in trace events]
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0hw/gpio/avr_gpio.c=C2=A0 =C2=A0| 26 +++++++++++++++++++++-----
=C2=A0hw/gpio/trace-events |=C2=A0 5 +++++
=C2=A02 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
index e4c7122e62c..29252d6ccfe 100644
--- a/hw/gpio/avr_gpio.c
+++ b/hw/gpio/avr_gpio.c
@@ -2,6 +2,7 @@
=C2=A0 * AVR processors GPIO registers emulation.
=C2=A0 *
=C2=A0 * Copyright (C) 2020 Heecheol Yang <heecheol.yang@outlook.com>
+ * Copyright (C) 2021 Niteesh Babu G S <niteesh.gs@gmail.com>
=C2=A0 *
=C2=A0 * This program is free software; you can redistribute it and/or
=C2=A0 * modify it under the terms of the GNU General Public License as
@@ -26,6 +27,12 @@
=C2=A0#include "hw/gpio/avr_gpio.h"
=C2=A0#include "hw/qdev-properties.h"
=C2=A0#include "migration/vmstate.h"
+#include "trace.h"
+
+static char port_name(AVRGPIOState *s)
+{
+=C2=A0 =C2=A0 return 'A' + s->id;
+}

=C2=A0static void avr_gpio_reset(DeviceState *dev)
=C2=A0{
@@ -47,32 +54,41 @@ static void avr_gpio_write_port(AVRGPIOState *s, uint64= _t value)

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (cur_ddr_pin_val && (cur_port_= pin_val !=3D new_port_pin_val)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_set_irq(s->out[pin]= , new_port_pin_val);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_avr_gpio_update_output_irq= (port_name(s), pin, new_port_pin_val);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0s->reg.port =3D value & s->reg.ddr;
=C2=A0}
=C2=A0static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned i= nt size)
=C2=A0{
+=C2=A0 =C2=A0 uint8_t val =3D 0;
=C2=A0 =C2=A0 =C2=A0AVRGPIOState *s =3D (AVRGPIOState *)opaque;
=C2=A0 =C2=A0 =C2=A0switch (offset) {
=C2=A0 =C2=A0 =C2=A0case GPIO_PIN:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 return s->reg.pin;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 val =3D s->reg.pin;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
=C2=A0 =C2=A0 =C2=A0case GPIO_DDR:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 return s->reg.ddr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 val =3D s->reg.ddr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
=C2=A0 =C2=A0 =C2=A0case GPIO_PORT:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 return s->reg.port;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 val =3D s->reg.port;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
=C2=A0 =C2=A0 =C2=A0default:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0g_assert_not_reached();
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 return 0;
+
+=C2=A0 =C2=A0 trace_avr_gpio_read(port_name(s), offset, val);
+=C2=A0 =C2=A0 return val;
=C2=A0}

=C2=A0static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t valu= e,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned int size)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0AVRGPIOState *s =3D (AVRGPIOState *)opaque;
-=C2=A0 =C2=A0 value =3D value & 0xF;
+=C2=A0 =C2=A0 value =3D value & 0xFF;
+
+=C2=A0 =C2=A0 trace_avr_gpio_write(port_name(s), offset, value);
=C2=A0 =C2=A0 =C2=A0switch (offset) {
=C2=A0 =C2=A0 =C2=A0case GPIO_PIN:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->reg.pin =3D value;
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index 46ab9323bd0..640834597a8 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -18,3 +18,8 @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offse= t 0x%" PRIx64 " value 0x%" P
=C2=A0sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%&q= uot; PRIx64 " value 0x%" PRIx64
=C2=A0sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi6= 4 " value %" PRIi64
=C2=A0sifive_gpio_update_output_irq(int64_t line, int64_t value) "line= %" PRIi64 " value %" PRIi64
+
+# avr_gpio.c
+avr_gpio_read(unsigned id, uint64_t offset, uint64_t r) "port %c offs= et 0x%" PRIx64 " value 0x%" PRIx64
+avr_gpio_write(unsigned id, uint64_t offset, uint64_t value) "port %c= offset 0x%" PRIx64 " value 0x%" PRIx64
+avr_gpio_update_output_irq(unsigned id, int64_t line, int64_t value) "= ;port %c pin %" PRIi64 " value %" PRIi64
--
2.26.2

--00000000000051f55805be2b223f--