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From: Brian Norris <computersforpeace@gmail.com>
To: linux-mtd@lists.infradead.org
Cc: Marek Vasut <marex@denx.de>,
	Brian Norris <computersforpeace@gmail.com>,
	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Subject: Re: [PATCH] mtd: m25p80: Micron SPI uses Macronix-style 4-byte addressing
Date: Fri, 9 Aug 2013 14:32:51 -0700	[thread overview]
Message-ID: <CAN8TOE_3i7WSi1XrO0OWa=EggacMOU+vGcHw26EEn84CN=f_KA@mail.gmail.com> (raw)
In-Reply-To: <1376072646-26089-1-git-send-email-computersforpeace@gmail.com>

On Fri, Aug 9, 2013 at 11:24 AM, Brian Norris
<computersforpeace@gmail.com> wrote:
> Quoting a Micron representative:
>
>   "Majority of our NOR that needs 4-byte addressing (256Mb or 32MB and
>    higher) enter and exit 4byte through B7h and E9h commands. The
>    N25Q256A7xxx and N25Q512A7xxx parts do not support 4-byte addressing
>    mode via B7h or E9h command."
>
> They further clarified that those that don't support the enter/exit
> opcodes (B7h/E9h) are manufactured specifically to come up by default in
> 4-byte mode. We don't need to treat those parts any diffently, as they
> will discard the EN4B opcode as a no-op.

A clarification: it seems that *all* large Micron SPI flash support
the B7h and E9h opcodes, just that some default to 4-byte addressing.
The patch stands as-is, but I'd replace this part of the changelog
with:

"Micron confirmed that all large (>16MiB) Micron SPI support the B7h
and E9h opcodes."

Thanks,
Brian

  parent reply	other threads:[~2013-08-09 21:33 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-08-09 18:24 [PATCH] mtd: m25p80: Micron SPI uses Macronix-style 4-byte addressing Brian Norris
2013-08-09 18:46 ` Marek Vasut
2013-08-12  2:44   ` Brian Norris
2013-08-12 14:06     ` Vivien Didelot
2013-08-09 21:32 ` Brian Norris [this message]
2013-08-17 19:31 ` Brian Norris

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