From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anand Moon Date: Sat, 21 Dec 2019 17:00:32 +0530 Subject: [U-Boot] [PATCH 1/4] mmc: meson-gx: Fix tx phase in the tuning process In-Reply-To: <1j5ziag5rl.fsf@starbuckisacylon.baylibre.com> References: <20191126211206.4537-1-linux.amoon@gmail.com> <20191126211206.4537-2-linux.amoon@gmail.com> <1j5ziag5rl.fsf@starbuckisacylon.baylibre.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Jerome / Neil, [...] > > I'm not quite sure I get what I should understand from this log. > > I can comment on the original patch though. > > I think you should keep the phase settings aligned with Linux. > Thanks for this inputs. > A) Among the exchange I had with amlogic, I got that there should always > be a phase shift of 180 degree between the core and Tx phase. > > B) So far, Core=180, Tx=0, Rx=0 has proven to be quite stable for all > the devices. I spent significant amount of time testing that. > I feel you are referring below in mainline kernel #define CLK_CORE_PHASE_MASK GENMASK(9, 8) #define CLK_TX_PHASE_MASK GENMASK(11, 10) #define CLK_RX_PHASE_MASK GENMASK(13, 12) /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ clk_reg = CLK_ALWAYS_ON(host); clk_reg |= CLK_DIV_MASK; clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0); clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0); writel(clk_reg, host->regs + SD_EMMC_CLOCK); So in the current u-boot host we are not setting the correct bits for clock tuning I have modified with above changes and was able to boot into my Odorid N2 on emmc. I will check this out on my Odroid C2 and sdcard and then submit the next version. > If that's not the case for the N2 under linux, please report it to the > related ML. If these settings works under Linux, then it is not the > problem and I don't think you should change them in u-boot. ---- clock is enabled (380953Hz) clock is enabled (25000000Hz) clock is enabled (52000000Hz) switch to partitions #0, OK mmc2(part 0) is current device Scanning mmc 2:1... Found U-Boot script /boot/boot.scr 745 bytes read in 1 ms (727.5 KiB/s) ## Executing script at 08000000 27445760 bytes read in 605 ms (43.3 MiB/s) 65829 bytes read in 3 ms (20.9 MiB/s) 7404738 bytes read in 164 ms (43.1 MiB/s) ## Flattened Device Tree blob at 08008000 -Anand