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I have to enable CONFIG_REGULATOR_DEBUG, See the logs below. [ 0.784121] reg-fixed-voltage vcc3v3-pi6c-03-regulator: vcc3v3_pi6c03 supplying 3300000uV [ 0.784430] vcc3v3_pcie: 3300 mV, disabled [0] https://pastebin.com/aEKQx1YZ > > No, it did not work on my board, see bool logs. > > [0] https://pastebin.com/Lk93VFxg > If you check the driver code it requires *data-line* and *num-lanes from the dts. [ 0.725985] phy phy-fe8c0000.phy.4: lane number 0, val 1 [ 0.726975] phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock failed 0x6890000, check input refclk and power supply [ 0.728172] phy phy-fe8c0000.phy.4: phy init failed --> -110 [ 0.728704] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110 > From the boot log, looks like ethernet is broken: > mdio_bus stmmac-0: MDIO device at address 0 is missing. > rk_gmac-dwmac fe010000.ethernet eth0: no phy at addr -1 > > Actually I had this problem too, and reusing the "snps, reset" > property solved it. What confuses me is am I doing something > wrong or there is something wrong with the device tree now? > Yep, I have the following changes that work to bring the Ethernet up. alarm@rock-3a:~/linux-next-5.y-devel$ git diff arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 097cee13885d..498b9b2af3ed 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -242,6 +242,11 @@ &gmac1 { assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <0 20000 100000>; + snps,reset-active-low; + phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; pinctrl-names = "default"; @@ -250,6 +255,8 @@ &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_rgmii_bus>; + tx_delay = <0x30>; + rx_delay = <0x10>; status = "okay"; }; @@ -559,14 +566,11 @@ &i2s1_8ch { }; &mdio1 { - rgmii_phy1: ethernet-phy@0 { + rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <0x1>; pinctrl-names = "default"; pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; }; }; Thanks -Anand _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A48B6C32771 for ; Wed, 28 Sep 2022 11:06:06 +0000 (UTC) DKIM-Signature: v=1; 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Wed, 28 Sep 2022 04:04:58 -0700 (PDT) MIME-Version: 1.0 References: <20220927181531.5546-1-amadeus@jmu.edu.cn> In-Reply-To: <20220927181531.5546-1-amadeus@jmu.edu.cn> From: Anand Moon Date: Wed, 28 Sep 2022 16:34:43 +0530 Message-ID: Subject: Re: [PATCH-next v1] arm64: dts: rockchip: Enable NVM Express PCIe controller on rock3a To: Chukun Pan Cc: heiko@sntech.de, robh+dt@kernel.org, michael.riesch@wolfvision.net, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220928_040459_919406_88EEC0E7 X-CRM114-Status: GOOD ( 22.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Chukun, On Tue, 27 Sept 2022 at 23:45, Chukun Pan wrote: > > Hi Anand, > > On 27-09-22, 19:16, Anand Moon wrote: > > > As per the schematic below pice support with 2 regulators > > > > VCC3V3_PCIE (SCT2250FPA) > > VCC3V3_PI6C_03 (PI6C557-03 is a spread spectrum clock generator > > supporting PCI Express and Ethernet requirements) > > > [0] https://dl.radxa.com/rock3/docs/hw/3a/rock3a_v1.3_sch.pdf > > Thanks for sharing, I rewrote this patch, can you try again? > No, It's not working on my board. I have to enable CONFIG_REGULATOR_DEBUG, See the logs below. [ 0.784121] reg-fixed-voltage vcc3v3-pi6c-03-regulator: vcc3v3_pi6c03 supplying 3300000uV [ 0.784430] vcc3v3_pcie: 3300 mV, disabled [0] https://pastebin.com/aEKQx1YZ > > No, it did not work on my board, see bool logs. > > [0] https://pastebin.com/Lk93VFxg > If you check the driver code it requires *data-line* and *num-lanes from the dts. [ 0.725985] phy phy-fe8c0000.phy.4: lane number 0, val 1 [ 0.726975] phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock failed 0x6890000, check input refclk and power supply [ 0.728172] phy phy-fe8c0000.phy.4: phy init failed --> -110 [ 0.728704] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110 > From the boot log, looks like ethernet is broken: > mdio_bus stmmac-0: MDIO device at address 0 is missing. > rk_gmac-dwmac fe010000.ethernet eth0: no phy at addr -1 > > Actually I had this problem too, and reusing the "snps, reset" > property solved it. What confuses me is am I doing something > wrong or there is something wrong with the device tree now? > Yep, I have the following changes that work to bring the Ethernet up. alarm@rock-3a:~/linux-next-5.y-devel$ git diff arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 097cee13885d..498b9b2af3ed 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -242,6 +242,11 @@ &gmac1 { assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <0 20000 100000>; + snps,reset-active-low; + phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; pinctrl-names = "default"; @@ -250,6 +255,8 @@ &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_rgmii_bus>; + tx_delay = <0x30>; + rx_delay = <0x10>; status = "okay"; }; @@ -559,14 +566,11 @@ &i2s1_8ch { }; &mdio1 { - rgmii_phy1: ethernet-phy@0 { + rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <0x1>; pinctrl-names = "default"; pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; }; }; Thanks -Anand _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28CC6C32771 for ; Wed, 28 Sep 2022 11:08:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233865AbiI1LIF (ORCPT ); Wed, 28 Sep 2022 07:08:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233469AbiI1LHm (ORCPT ); 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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Chukun, On Tue, 27 Sept 2022 at 23:45, Chukun Pan wrote: > > Hi Anand, > > On 27-09-22, 19:16, Anand Moon wrote: > > > As per the schematic below pice support with 2 regulators > > > > VCC3V3_PCIE (SCT2250FPA) > > VCC3V3_PI6C_03 (PI6C557-03 is a spread spectrum clock generator > > supporting PCI Express and Ethernet requirements) > > > [0] https://dl.radxa.com/rock3/docs/hw/3a/rock3a_v1.3_sch.pdf > > Thanks for sharing, I rewrote this patch, can you try again? > No, It's not working on my board. I have to enable CONFIG_REGULATOR_DEBUG, See the logs below. [ 0.784121] reg-fixed-voltage vcc3v3-pi6c-03-regulator: vcc3v3_pi6c03 supplying 3300000uV [ 0.784430] vcc3v3_pcie: 3300 mV, disabled [0] https://pastebin.com/aEKQx1YZ > > No, it did not work on my board, see bool logs. > > [0] https://pastebin.com/Lk93VFxg > If you check the driver code it requires *data-line* and *num-lanes from the dts. [ 0.725985] phy phy-fe8c0000.phy.4: lane number 0, val 1 [ 0.726975] phy phy-fe8c0000.phy.4: rockchip_p3phy_rk3568_init: lock failed 0x6890000, check input refclk and power supply [ 0.728172] phy phy-fe8c0000.phy.4: phy init failed --> -110 [ 0.728704] rockchip-dw-pcie: probe of 3c0800000.pcie failed with error -110 > From the boot log, looks like ethernet is broken: > mdio_bus stmmac-0: MDIO device at address 0 is missing. > rk_gmac-dwmac fe010000.ethernet eth0: no phy at addr -1 > > Actually I had this problem too, and reusing the "snps, reset" > property solved it. What confuses me is am I doing something > wrong or there is something wrong with the device tree now? > Yep, I have the following changes that work to bring the Ethernet up. alarm@rock-3a:~/linux-next-5.y-devel$ git diff arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 097cee13885d..498b9b2af3ed 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -242,6 +242,11 @@ &gmac1 { assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-delays-us = <0 20000 100000>; + snps,reset-active-low; + phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; pinctrl-names = "default"; @@ -250,6 +255,8 @@ &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk &gmac1m1_rgmii_bus>; + tx_delay = <0x30>; + rx_delay = <0x10>; status = "okay"; }; @@ -559,14 +566,11 @@ &i2s1_8ch { }; &mdio1 { - rgmii_phy1: ethernet-phy@0 { + rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; + reg = <0x1>; pinctrl-names = "default"; pinctrl-0 = <ð_phy_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; }; }; Thanks -Anand