From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752997AbbJMDtl (ORCPT ); Mon, 12 Oct 2015 23:49:41 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:35691 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751039AbbJMDtj (ORCPT ); Mon, 12 Oct 2015 23:49:39 -0400 MIME-Version: 1.0 In-Reply-To: <561C7DF1.6000609@samsung.com> References: <1444578364-1384-1-git-send-email-linux.amoon@gmail.com> <1444578364-1384-3-git-send-email-linux.amoon@gmail.com> <561B48B7.1040201@samsung.com> <561C4CEE.3050905@samsung.com> <561C7DF1.6000609@samsung.com> From: Anand Moon Date: Tue, 13 Oct 2015 09:19:17 +0530 Message-ID: Subject: Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support To: Krzysztof Kozlowski Cc: Kukjin Kim , Javier Martinez Canillas , Lukasz Majewski , Jaehoon Chung , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "linux-samsung-soc@vger.kernel.org" , Linux Kernel Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, On 13 October 2015 at 09:13, Krzysztof Kozlowski wrote: > On 13.10.2015 12:08, Anand Moon wrote: >> Hi Krzysztof, >> >> On 13 October 2015 at 05:44, Krzysztof Kozlowski >> wrote: >>> On 13.10.2015 00:32, Anand Moon wrote: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>>> >>>> Setting this DDR50 capability give me this error. That's the reason to >>>> drop this capability. >>> >>> But you mentioned it in commit message! "Added support for UHS-I ... >>> (DDR50)" >>> >>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>> and SDR104 are really supported". >>> >> >> These changes are related to the microSD card capabilities. >> So SDR50 have better frequency over DDR50. On the same Sandisk card. >> >> When the card select the capability for DDR50 >> --------------------------------------------------- >> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.009179] mmcblk0: error -110 sending status command, retrying >> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >> response 0x900, card status 0x900 >> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >> cmd response 0x900, card status 0x0 >> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 400000Hz, actual 396825HZ div = 63) >> [ 4.067770] Console: switching to colour frame buffer device 274x77 >> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.099692] mmc1: tried to reset card >> [ 4.101332] mmcblk0: p1 p2 >> >> >> When the card select the capability for SDR50 >> --------------------------------------------------------------------------------- >> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >> 100000000Hz, actual 100000000HZ div = 0) >> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 2.461743] mmcblk0: p1 p2 >> >> Which will relate to better read/write speed. > > Which is not an answer to my question. To none of my previous questions. OK, you are correct.Just ignore these changes. -Anand Moon > > Best regards, > Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anand Moon Subject: Re: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support Date: Tue, 13 Oct 2015 09:19:17 +0530 Message-ID: References: <1444578364-1384-1-git-send-email-linux.amoon@gmail.com> <1444578364-1384-3-git-send-email-linux.amoon@gmail.com> <561B48B7.1040201@samsung.com> <561C4CEE.3050905@samsung.com> <561C7DF1.6000609@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <561C7DF1.6000609-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Krzysztof Kozlowski Cc: Kukjin Kim , Javier Martinez Canillas , Lukasz Majewski , Jaehoon Chung , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, "linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Linux Kernel List-Id: devicetree@vger.kernel.org Hi Krzysztof, On 13 October 2015 at 09:13, Krzysztof Kozlowski wrote: > On 13.10.2015 12:08, Anand Moon wrote: >> Hi Krzysztof, >> >> On 13 October 2015 at 05:44, Krzysztof Kozlowski >> wrote: >>> On 13.10.2015 00:32, Anand Moon wrote: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>>> >>>> Setting this DDR50 capability give me this error. That's the reason to >>>> drop this capability. >>> >>> But you mentioned it in commit message! "Added support for UHS-I ... >>> (DDR50)" >>> >>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>> and SDR104 are really supported". >>> >> >> These changes are related to the microSD card capabilities. >> So SDR50 have better frequency over DDR50. On the same Sandisk card. >> >> When the card select the capability for DDR50 >> --------------------------------------------------- >> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.009179] mmcblk0: error -110 sending status command, retrying >> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >> response 0x900, card status 0x900 >> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >> cmd response 0x900, card status 0x0 >> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 400000Hz, actual 396825HZ div = 63) >> [ 4.067770] Console: switching to colour frame buffer device 274x77 >> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.099692] mmc1: tried to reset card >> [ 4.101332] mmcblk0: p1 p2 >> >> >> When the card select the capability for SDR50 >> --------------------------------------------------------------------------------- >> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >> 100000000Hz, actual 100000000HZ div = 0) >> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 2.461743] mmcblk0: p1 p2 >> >> Which will relate to better read/write speed. > > Which is not an answer to my question. To none of my previous questions. OK, you are correct.Just ignore these changes. -Anand Moon > > Best regards, > Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux.amoon@gmail.com (Anand Moon) Date: Tue, 13 Oct 2015 09:19:17 +0530 Subject: [PATCH 3/3] ARM: dts: exynos5422-odroidxu3: Added UHS-I bus speed support In-Reply-To: <561C7DF1.6000609@samsung.com> References: <1444578364-1384-1-git-send-email-linux.amoon@gmail.com> <1444578364-1384-3-git-send-email-linux.amoon@gmail.com> <561B48B7.1040201@samsung.com> <561C4CEE.3050905@samsung.com> <561C7DF1.6000609@samsung.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Krzysztof, On 13 October 2015 at 09:13, Krzysztof Kozlowski wrote: > On 13.10.2015 12:08, Anand Moon wrote: >> Hi Krzysztof, >> >> On 13 October 2015 at 05:44, Krzysztof Kozlowski >> wrote: >>> On 13.10.2015 00:32, Anand Moon wrote: >>>> Hi Krzysztof, >>>> >>>> On 12 October 2015 at 11:14, Krzysztof Kozlowski >>>> wrote: >>>>> On 12.10.2015 00:46, Anand Moon wrote: >>>>>> Added support for UHS-I bus speed 50MB/s (SDR50, DDR50) 104MB/s (SDR104) >>>>> >>>>> This description is not entirely correct. The MMC driver already >>>>> supports these UHS speeds (you did not any code) so you rather enabled >>>>> it (description of bindings says "is supported"). >>>>> >>>>> You mentioned DDR50 but I don't see respective property below. >>>>> >>>>> How do you know that these modes are really supported? I don't know. Can >>>>> you convince me? >>>> >>>> Setting this DDR50 capability give me this error. That's the reason to >>>> drop this capability. >>> >>> But you mentioned it in commit message! "Added support for UHS-I ... >>> (DDR50)" >>> >>> In the same time dropping DDR50 is not an sufficient proof that "SDR50 >>> and SDR104 are really supported". >>> >> >> These changes are related to the microSD card capabilities. >> So SDR50 have better frequency over DDR50. On the same Sandisk card. >> >> When the card select the capability for DDR50 >> --------------------------------------------------- >> [ 4.001477] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.001604] mmc1: new ultra high speed DDR50 SDHC card at address aaaa >> [ 4.004505] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 4.009179] mmcblk0: error -110 sending status command, retrying >> [ 4.009271] mmcblk0: error -115 sending stop command, original cmd >> response 0x900, card status 0x900 >> [ 4.009275] mmcblk0: error -84 transferring data, sector 0, nr 8, >> cmd response 0x900, card status 0x0 >> [ 4.025563] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 400000Hz, actual 396825HZ div = 63) >> [ 4.067770] Console: switching to colour frame buffer device 274x77 >> [ 4.098782] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot >> req 50000000Hz, actual 50000000HZ div = 0) >> [ 4.099692] mmc1: tried to reset card >> [ 4.101332] mmcblk0: p1 p2 >> >> >> When the card select the capability for SDR50 >> --------------------------------------------------------------------------------- >> [ 2.439806] mmc_host mmc1: Bus speed (slot 0) = 100000000Hz (slot req >> 100000000Hz, actual 100000000HZ div = 0) >> [ 2.449729] mmc1: new ultra high speed SDR50 SDHC card at address aaaa >> [ 2.455984] mmcblk0: mmc1:aaaa SL32G 29.7 GiB >> [ 2.461743] mmcblk0: p1 p2 >> >> Which will relate to better read/write speed. > > Which is not an answer to my question. To none of my previous questions. OK, you are correct.Just ignore these changes. -Anand Moon > > Best regards, > Krzysztof