From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 944AAC433EF for ; Fri, 22 Oct 2021 14:25:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7D22560E96 for ; Fri, 22 Oct 2021 14:25:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232949AbhJVO1m (ORCPT ); Fri, 22 Oct 2021 10:27:42 -0400 Received: from mail-pf1-f175.google.com ([209.85.210.175]:46723 "EHLO mail-pf1-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232276AbhJVO1l (ORCPT ); Fri, 22 Oct 2021 10:27:41 -0400 Received: by mail-pf1-f175.google.com with SMTP id x66so3742087pfx.13; Fri, 22 Oct 2021 07:25:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jorqKoNvCog+RdJEWLLzk4/vugG3Lx6Xwa7r7jPCqTI=; b=FCdcn7vVuIjicwvIn3P4ZQHYD/4ly7txPGIskT4FNCudWWHaUJsbAzrx7pfW6LL83A TAhpi3CIUjv5qXNP9a8WpS1/8ylJur1VPW2sRE/aufw+28LLfAWw4OyczRadPZVQ+mbR N3cNbhPQ0/vudTJKhugvCJgY7JYdB7ZfyeS+ADjoMd1PVZ/leJ3De19ewjZXwUGFtxTV U6ETQuoioD0LK7Ba2iQ5KlwtkkYFnzn0mAF03QL66xz/jRs+yvxgiNvrmO1rjAXypm/6 Gzrh6cBcD/uD9cgnInElbp1uR/RO2uGJHQvs/AbMQdUkjGK0+E2svQXb6RAhvwFaUtud yYsQ== X-Gm-Message-State: AOAM530C1wF5Y63M0BPsndjMMIeeyk2N+P3SV6WXE8ySGa9sDQ3js9CC QXhHofQz+fu2jjHpBRx8Zl+8UjQzBZZi0I0sMJfVnYyjZZVsIA== X-Google-Smtp-Source: ABdhPJwwiGgg/wAhh2MuTJi/0OlJOC3w8grm3LkhekM9ZxjuDcMopYi54hXrYFPVSp69WJyB7UqQZkgeS1a1t8VrapI= X-Received: by 2002:a62:5257:0:b0:44c:ed84:350a with SMTP id g84-20020a625257000000b0044ced84350amr12576754pfb.79.1634912723745; Fri, 22 Oct 2021 07:25:23 -0700 (PDT) MIME-Version: 1.0 References: <20211021174223.43310-1-kernel@esmil.dk> <20211021174223.43310-10-kernel@esmil.dk> In-Reply-To: From: Emil Renner Berthing Date: Fri, 22 Oct 2021 16:25:12 +0200 Message-ID: Subject: Re: [PATCH v2 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver To: Andy Shevchenko Cc: linux-riscv , devicetree , linux-clk , "open list:GPIO SUBSYSTEM" , "open list:SERIAL DRIVERS" , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Fri, 22 Oct 2021 at 15:39, Andy Shevchenko wrote: > On Fri, Oct 22, 2021 at 4:35 PM Emil Renner Berthing wrote: > > On Fri, 22 Oct 2021 at 14:56, Andy Shevchenko wrote: > > > On Thu, Oct 21, 2021 at 8:43 PM Emil Renner Berthing wrote: > > ... > > > > Why all these ugly % 32 against constants? > > > > Because the JH7100_RST_ values goes higher than 31. There is a > > BIT_MASK macro, but that does % BITS_PER_LONG and this is a 64bit > > machine. > > And? It's exactly what you have to use! So you want me to use an unsigned long array or DECLARE_BITMAP and juggle two different index and bit offsets? Also is there a macro for handling that we'd then need 4 commas on 32bit COMPILE_TEST and 2 commas on 64bit? If you have some other way in mind you'll have to be a lot more explicit again. The point of the jh7100_reset_asserted array is that it exactly mirrors the values of the status registers when the lines are asserted. Maybe writing it like this would be more explicit: static const u32 jh7100_reset_asserted[4] = { /* STATUS0 register */ BIT(JH7100_RST_U74 % 32) | BIT(JH7100_RST_VP6_DRESET % 32) | BIT(JH7100_RST_VP6_BRESET % 32), /* STATUS1 register */ BIT(JH7100_RST_HIFI4_DRESET % 32) | BIT(JH7100_RST_HIFI4_BRESET % 32), /* STATUS2 register */ BIT(JH7100_RST_E24 % 32), /* STATUS3 register */ 0, }; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76C78C433F5 for ; Fri, 22 Oct 2021 14:25:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2622860E96 for ; Fri, 22 Oct 2021 14:25:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2622860E96 Authentication-Results: mail.kernel.org; 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Fri, 22 Oct 2021 07:25:23 -0700 (PDT) MIME-Version: 1.0 References: <20211021174223.43310-1-kernel@esmil.dk> <20211021174223.43310-10-kernel@esmil.dk> In-Reply-To: From: Emil Renner Berthing Date: Fri, 22 Oct 2021 16:25:12 +0200 Message-ID: Subject: Re: [PATCH v2 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver To: Andy Shevchenko Cc: linux-riscv , devicetree , linux-clk , "open list:GPIO SUBSYSTEM" , "open list:SERIAL DRIVERS" , Palmer Dabbelt , Paul Walmsley , Rob Herring , Michael Turquette , Stephen Boyd , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Linus Walleij , Greg Kroah-Hartman , Daniel Lezcano , Andy Shevchenko , Jiri Slaby , Maximilian Luz , Sagar Kadam , Drew Fustini , Geert Uytterhoeven , Michael Zhu , Fu Wei , Anup Patel , Atish Patra , Matteo Croce , Linux Kernel Mailing List X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211022_072525_268939_6AE45D02 X-CRM114-Status: GOOD ( 15.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, 22 Oct 2021 at 15:39, Andy Shevchenko wrote: > On Fri, Oct 22, 2021 at 4:35 PM Emil Renner Berthing wrote: > > On Fri, 22 Oct 2021 at 14:56, Andy Shevchenko wrote: > > > On Thu, Oct 21, 2021 at 8:43 PM Emil Renner Berthing wrote: > > ... > > > > Why all these ugly % 32 against constants? > > > > Because the JH7100_RST_ values goes higher than 31. There is a > > BIT_MASK macro, but that does % BITS_PER_LONG and this is a 64bit > > machine. > > And? It's exactly what you have to use! So you want me to use an unsigned long array or DECLARE_BITMAP and juggle two different index and bit offsets? Also is there a macro for handling that we'd then need 4 commas on 32bit COMPILE_TEST and 2 commas on 64bit? If you have some other way in mind you'll have to be a lot more explicit again. The point of the jh7100_reset_asserted array is that it exactly mirrors the values of the status registers when the lines are asserted. Maybe writing it like this would be more explicit: static const u32 jh7100_reset_asserted[4] = { /* STATUS0 register */ BIT(JH7100_RST_U74 % 32) | BIT(JH7100_RST_VP6_DRESET % 32) | BIT(JH7100_RST_VP6_BRESET % 32), /* STATUS1 register */ BIT(JH7100_RST_HIFI4_DRESET % 32) | BIT(JH7100_RST_HIFI4_BRESET % 32), /* STATUS2 register */ BIT(JH7100_RST_E24 % 32), /* STATUS3 register */ 0, }; _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv