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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=RV9abJpc/Fo58oWk1J7NQlZY21GsuG1jmymWDui8Jso=; b=ZnbyX18ccXIlh61uTZkGCkP767ubXOxc0LzpEukfM+rX3e4QPLpCEEpnAXrOIIcLdk SIinpCdmnyN4mPI63tirGkVp10DEN42am/ENlF5J3/snxBu09zDYzSQG/EQchtkdMcrm GKS/iauD6zPUAESSU9pwfONIyjptimm0ElBvtqvz/8CtAjqRx7zTfnDfSJ1W665UeJM7 /JLMZQuhMEKreCGEr31uj89zbDN1SlvFm1W1m140uzPPOq1QYoYnHGxnRUIdj94+IAKd QiJEJ6+Gi0wQC3hbetf53gE9W553ru631tGgK1zNlKjUSl92dtKF80muCiblke9SA7F0 F/4w== X-Gm-Message-State: ABuFfoh4HeXGsjJWSPf9Ph+yEtUhltufgzbC10lJqpyeYa55XkrZIKjy iWYS1Noon60tOk2pi0dGGa31oUp4YYoithhJugU= X-Google-Smtp-Source: ACcGV62v75zXJxjwoIDlGI7nyRx6PACjrkbZOoNZS0yIgMzhANsNcwLVKamcpUErrmFtpGX6pdsZZHmiswcna5TjyiA= X-Received: by 2002:a2e:93c4:: with SMTP id p4-v6mr2694146ljh.150.1537552851268; Fri, 21 Sep 2018 11:00:51 -0700 (PDT) MIME-Version: 1.0 References: <1537367527-20773-1-git-send-email-jim2101024@gmail.com> <1537367527-20773-3-git-send-email-jim2101024@gmail.com> In-Reply-To: From: Jim Quinlan Date: Fri, 21 Sep 2018 14:00:39 -0400 Message-ID: Subject: Re: [PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device To: Jonas Gorski Cc: linux-kernel@vger.kernel.org, Bjorn Helgaas , Rob Herring , Mark Rutland , Brian Norris , Gregory Fong , Florian Fainelli , bcm-kernel-feedback-list , linux-pci , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Christoph Hellwig Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 20, 2018 at 5:06 AM Jonas Gorski wrote: > > On 19 September 2018 at 16:31, Jim Quinlan wrote: > > The DT bindings description of the Brcmstb PCIe device is described. > > This node can be used by almost all Broadcom settop box chips, using > > ARM, ARM64, or MIPS CPU architectures. > > Oh, hey, *one* email made it finally through :P Sigh, I'm still having email issues, my apologies. > > > > > Signed-off-by: Jim Quinlan > > Acked-by: Rob Herring > > --- > > .../devicetree/bindings/pci/brcmstb-pcie.txt | 59 ++++++++++++++++++++++ > > 1 file changed, 59 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > > > diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > new file mode 100644 > > index 0000000..a1a9ad5 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > @@ -0,0 +1,59 @@ > > +Brcmstb PCIe Host Controller Device Tree Bindings > > + > > +Required Properties: > > +- compatible > > + "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs. > > + "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs. > > + "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including > > + the 7278). > > + "brcm,bcm7278-pcie" -- for 7278 family ARM-based SOCs. > > + > > +- reg -- the register start address and length for the PCIe reg block. > > +- interrupts -- two interrupts are specified; the first interrupt is for > > + the PCI host controller and the second is for MSI if the built-in > > + MSI controller is to be used. > > +- interrupt-names -- names of the interrupts (above): "pcie" and "msi". > > +- #address-cells -- set to <3>. > > +- #size-cells -- set to <2>. > > +- #interrupt-cells: set to <1>. > > +- interrupt-map-mask and interrupt-map, standard PCI properties to define the > > + mapping of the PCIe interface to interrupt numbers. > > +- ranges: ranges for the PCI memory and I/O regions. > > +- linux,pci-domain -- should be unique per host controller. > > + > > +Optional Properties: > > +- clocks -- phandle of pcie clock. > > +- clock-names -- set to "sw_pcie" if clocks is used. > > +- dma-ranges -- Specifies the inbound memory mapping regions when > > + an "identity map" is not possible. > > +- msi-controller -- this property is typically specified to have the > > + PCIe controller use its internal MSI controller. > > +- msi-parent -- set to use an external MSI interrupt controller. > > +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking. > > +- max-link-speed -- (integer) indicates desired generation of link: > > + 1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3). > > + > > +Example Node: > > + > > +pcie0: pcie@f0460000 { > > + reg = <0x0 0xf0460000 0x0 0x9310>; > > + interrupts = <0x0 0x0 0x4>; > > Your binding says two interrupts, your example has three - what's the > third interrupt for? Actually that's a single interrupt with three cells. I need to add another interrupt. Note that we have #interrupt-cells set to 1 because that is for the legacy interrupts given in the interrupt-map. > Also you define the same for MSI and PCIe (I assume) - is that expected? No, these will be updated to two different interrupts. Are there systems where they are > different? I would expect the msi interrupt to be optional for the > case where its the same as the pcie one, and only required if it is > different. > > Also your binding requires an interrupt-names propery, but it's > missing from the example. Will fix. Thanks, Jim > > > + compatible = "brcm,bcm7445-pcie"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000 > > + 0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &intc 0 47 3 > > + 0 0 0 2 &intc 0 48 3 > > + 0 0 0 3 &intc 0 49 3 > > + 0 0 0 4 &intc 0 50 3>; > > + clocks = <&sw_pcie0>; > > + clock-names = "sw_pcie"; > > + msi-parent = <&pcie0>; /* use PCIe's internal MSI controller */ > > + msi-controller; /* use PCIe's internal MSI controller */ > > + brcm,ssc; > > + max-link-speed = <1>; > > + linux,pci-domain = <0>; > > + }; > > -- > > 1.9.0.138.g2de3478 > > > > Regards > Jonas From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jim Quinlan Subject: Re: [PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device Date: Fri, 21 Sep 2018 14:00:39 -0400 Message-ID: References: <1537367527-20773-1-git-send-email-jim2101024@gmail.com> <1537367527-20773-3-git-send-email-jim2101024@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Jonas Gorski Cc: linux-kernel@vger.kernel.org, Bjorn Helgaas , Rob Herring , Mark Rutland , Brian Norris , Gregory Fong , Florian Fainelli , bcm-kernel-feedback-list , linux-pci , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Christoph Hellwig List-Id: devicetree@vger.kernel.org On Thu, Sep 20, 2018 at 5:06 AM Jonas Gorski wrote: > > On 19 September 2018 at 16:31, Jim Quinlan wrote: > > The DT bindings description of the Brcmstb PCIe device is described. > > This node can be used by almost all Broadcom settop box chips, using > > ARM, ARM64, or MIPS CPU architectures. > > Oh, hey, *one* email made it finally through :P Sigh, I'm still having email issues, my apologies. > > > > > Signed-off-by: Jim Quinlan > > Acked-by: Rob Herring > > --- > > .../devicetree/bindings/pci/brcmstb-pcie.txt | 59 ++++++++++++++++++++++ > > 1 file changed, 59 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > > > diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > new file mode 100644 > > index 0000000..a1a9ad5 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > @@ -0,0 +1,59 @@ > > +Brcmstb PCIe Host Controller Device Tree Bindings > > + > > +Required Properties: > > +- compatible > > + "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs. > > + "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs. > > + "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including > > + the 7278). > > + "brcm,bcm7278-pcie" -- for 7278 family ARM-based SOCs. > > + > > +- reg -- the register start address and length for the PCIe reg block. > > +- interrupts -- two interrupts are specified; the first interrupt is for > > + the PCI host controller and the second is for MSI if the built-in > > + MSI controller is to be used. > > +- interrupt-names -- names of the interrupts (above): "pcie" and "msi". > > +- #address-cells -- set to <3>. > > +- #size-cells -- set to <2>. > > +- #interrupt-cells: set to <1>. > > +- interrupt-map-mask and interrupt-map, standard PCI properties to define the > > + mapping of the PCIe interface to interrupt numbers. > > +- ranges: ranges for the PCI memory and I/O regions. > > +- linux,pci-domain -- should be unique per host controller. > > + > > +Optional Properties: > > +- clocks -- phandle of pcie clock. > > +- clock-names -- set to "sw_pcie" if clocks is used. > > +- dma-ranges -- Specifies the inbound memory mapping regions when > > + an "identity map" is not possible. > > +- msi-controller -- this property is typically specified to have the > > + PCIe controller use its internal MSI controller. > > +- msi-parent -- set to use an external MSI interrupt controller. > > +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking. > > +- max-link-speed -- (integer) indicates desired generation of link: > > + 1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3). > > + > > +Example Node: > > + > > +pcie0: pcie@f0460000 { > > + reg = <0x0 0xf0460000 0x0 0x9310>; > > + interrupts = <0x0 0x0 0x4>; > > Your binding says two interrupts, your example has three - what's the > third interrupt for? Actually that's a single interrupt with three cells. I need to add another interrupt. Note that we have #interrupt-cells set to 1 because that is for the legacy interrupts given in the interrupt-map. > Also you define the same for MSI and PCIe (I assume) - is that expected? No, these will be updated to two different interrupts. Are there systems where they are > different? I would expect the msi interrupt to be optional for the > case where its the same as the pcie one, and only required if it is > different. > > Also your binding requires an interrupt-names propery, but it's > missing from the example. Will fix. Thanks, Jim > > > + compatible = "brcm,bcm7445-pcie"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000 > > + 0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &intc 0 47 3 > > + 0 0 0 2 &intc 0 48 3 > > + 0 0 0 3 &intc 0 49 3 > > + 0 0 0 4 &intc 0 50 3>; > > + clocks = <&sw_pcie0>; > > + clock-names = "sw_pcie"; > > + msi-parent = <&pcie0>; /* use PCIe's internal MSI controller */ > > + msi-controller; /* use PCIe's internal MSI controller */ > > + brcm,ssc; > > + max-link-speed = <1>; > > + linux,pci-domain = <0>; > > + }; > > -- > > 1.9.0.138.g2de3478 > > > > Regards > Jonas From mboxrd@z Thu Jan 1 00:00:00 1970 From: jim2101024@gmail.com (Jim Quinlan) Date: Fri, 21 Sep 2018 14:00:39 -0400 Subject: [PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device In-Reply-To: References: <1537367527-20773-1-git-send-email-jim2101024@gmail.com> <1537367527-20773-3-git-send-email-jim2101024@gmail.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Sep 20, 2018 at 5:06 AM Jonas Gorski wrote: > > On 19 September 2018 at 16:31, Jim Quinlan wrote: > > The DT bindings description of the Brcmstb PCIe device is described. > > This node can be used by almost all Broadcom settop box chips, using > > ARM, ARM64, or MIPS CPU architectures. > > Oh, hey, *one* email made it finally through :P Sigh, I'm still having email issues, my apologies. > > > > > Signed-off-by: Jim Quinlan > > Acked-by: Rob Herring > > --- > > .../devicetree/bindings/pci/brcmstb-pcie.txt | 59 ++++++++++++++++++++++ > > 1 file changed, 59 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > > > diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > new file mode 100644 > > index 0000000..a1a9ad5 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt > > @@ -0,0 +1,59 @@ > > +Brcmstb PCIe Host Controller Device Tree Bindings > > + > > +Required Properties: > > +- compatible > > + "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs. > > + "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs. > > + "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including > > + the 7278). > > + "brcm,bcm7278-pcie" -- for 7278 family ARM-based SOCs. > > + > > +- reg -- the register start address and length for the PCIe reg block. > > +- interrupts -- two interrupts are specified; the first interrupt is for > > + the PCI host controller and the second is for MSI if the built-in > > + MSI controller is to be used. > > +- interrupt-names -- names of the interrupts (above): "pcie" and "msi". > > +- #address-cells -- set to <3>. > > +- #size-cells -- set to <2>. > > +- #interrupt-cells: set to <1>. > > +- interrupt-map-mask and interrupt-map, standard PCI properties to define the > > + mapping of the PCIe interface to interrupt numbers. > > +- ranges: ranges for the PCI memory and I/O regions. > > +- linux,pci-domain -- should be unique per host controller. > > + > > +Optional Properties: > > +- clocks -- phandle of pcie clock. > > +- clock-names -- set to "sw_pcie" if clocks is used. > > +- dma-ranges -- Specifies the inbound memory mapping regions when > > + an "identity map" is not possible. > > +- msi-controller -- this property is typically specified to have the > > + PCIe controller use its internal MSI controller. > > +- msi-parent -- set to use an external MSI interrupt controller. > > +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking. > > +- max-link-speed -- (integer) indicates desired generation of link: > > + 1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3). > > + > > +Example Node: > > + > > +pcie0: pcie at f0460000 { > > + reg = <0x0 0xf0460000 0x0 0x9310>; > > + interrupts = <0x0 0x0 0x4>; > > Your binding says two interrupts, your example has three - what's the > third interrupt for? Actually that's a single interrupt with three cells. I need to add another interrupt. Note that we have #interrupt-cells set to 1 because that is for the legacy interrupts given in the interrupt-map. > Also you define the same for MSI and PCIe (I assume) - is that expected? No, these will be updated to two different interrupts. Are there systems where they are > different? I would expect the msi interrupt to be optional for the > case where its the same as the pcie one, and only required if it is > different. > > Also your binding requires an interrupt-names propery, but it's > missing from the example. Will fix. Thanks, Jim > > > + compatible = "brcm,bcm7445-pcie"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000 > > + 0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &intc 0 47 3 > > + 0 0 0 2 &intc 0 48 3 > > + 0 0 0 3 &intc 0 49 3 > > + 0 0 0 4 &intc 0 50 3>; > > + clocks = <&sw_pcie0>; > > + clock-names = "sw_pcie"; > > + msi-parent = <&pcie0>; /* use PCIe's internal MSI controller */ > > + msi-controller; /* use PCIe's internal MSI controller */ > > + brcm,ssc; > > + max-link-speed = <1>; > > + linux,pci-domain = <0>; > > + }; > > -- > > 1.9.0.138.g2de3478 > > > > Regards > Jonas