From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCE71C433EF for ; Thu, 2 Sep 2021 20:19:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B0F66112F for ; Thu, 2 Sep 2021 20:19:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7B0F66112F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bsdimp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLtBi-0001OV-Kz for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 16:19:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40066) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLt8t-00047M-58 for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:16:59 -0400 Received: from mail-ua1-x930.google.com ([2607:f8b0:4864:20::930]:41848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLt8p-0007Iu-W2 for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:16:58 -0400 Received: by mail-ua1-x930.google.com with SMTP id 75so1574249uav.8 for ; Thu, 02 Sep 2021 13:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=PPnlERc7u6MmKGlf0skuXfDJNggzkZn3z7puXsTnSGI=; b=gXFelTolWhXcGwOUQ8qd4G5wX34KjIcx/HGCdyzFHXafkuzeX148ceKMgpiDczKY9s a2ki2Z2b5yKfxZWrnBEFsNOk2tMNCIGTuxgJz2E2FouW/iYHTMiyuIlj1CcivGs8AjO5 vz9b23EbkqCDfvEjOdaLATg2kumJADmlW2Xzqvtd5tkh5slougPyKrUneZfrJM1bW6Ge 1K8jLiu7C9HVGbV46SnMby8C7TI+KI5kbBkOx9RG3IZ1xDdiU3T/Txid4m4D18WhMQ00 2dTQ3ZIge8CS3eNu4ZeZQ3jrSSQ7sFdO/vmHLTaeTMxDSUShpkUeFZocZ3KuoqcNJVtY aGCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PPnlERc7u6MmKGlf0skuXfDJNggzkZn3z7puXsTnSGI=; b=eILdIFrdauSN1gFZ/glbY/FHk8ylCGtl6B4rTW+jSrzsDrcU+i3STPAsYmsaeBG4wm ZFnbth1PcCA+AgaSPdXJpbi7Pho6AsUAE9NXmjY1ey7oT4cbU059qL3ufvah5uV+1UB2 sm8QOL9mBsAfxr7t8wzOSRRskRnUwwm3T7lidUPbxdlJY78yhNL7TtUA167tfUoCa3yi Zf2TEwsrdQBxjcSpyeTk4jMshiXmgmf1S7MKhc5Iz/ge6EhQiS+3U5PiOaPGGI32qfaN txDAZCKbvFyeVgQ8NGSgPN/3/qphL5+BxriFXIxwLR0q3mCBsFnt8IOBvTe3oGySLBCa ZmxQ== X-Gm-Message-State: AOAM532kg/u45N6KgbACm3BKxNnUj3hSImXQqc6TdUNdKbZdXX5gx9Oc ih78RuAxHuIqPHqzvKPwfYHukmp5CwzOogtZfhsziA== X-Google-Smtp-Source: ABdhPJynXdHCd8eJG54f42eLbPaOcq95rPiXaffj04QawshNpG98LF9S9cKxHtovEsQOEpoM4iSJy+rjGXJyjS4Cvh4= X-Received: by 2002:ab0:3413:: with SMTP id z19mr59626uap.39.1630613814846; Thu, 02 Sep 2021 13:16:54 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-9-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-9-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:16:44 -0600 Message-ID: Subject: Re: [PATCH 08/24] target/avr: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="00000000000033378f05cb08dd96" Received-SPF: none client-ip=2607:f8b0:4864:20::930; envelope-from=wlosh@bsdimp.com; helo=mail-ua1-x930.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bin Meng , Mark Cave-Ayland , QEMU Developers , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , qemu-ppc , Artyom Tarasenko , Aleksandar Rikalo , Eduardo Habkost , Kyle Evans , Richard Henderson , Greg Kurz , qemu-arm , Michael Rolnik , Stafford Horne , David Gibson , qemu-riscv@nongnu.org, Chris Wulff , Laurent Vivier , Palmer Dabbelt , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000033378f05cb08dd96 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/avr/cpu.h | 2 ++ > target/avr/cpu.c | 2 +- > target/avr/helper.c | 2 ++ > 3 files changed, 5 insertions(+), 1 deletion(-) > Reviewed-by: Warner Losh > diff --git a/target/avr/cpu.h b/target/avr/cpu.h > index 93e3faa0a98..6f8c0ffd770 100644 > --- a/target/avr/cpu.h > +++ b/target/avr/cpu.h > @@ -156,8 +156,10 @@ typedef struct AVRCPU { > > extern const struct VMStateDescription vms_avr_cpu; > > +#ifndef CONFIG_USER_ONLY > void avr_cpu_do_interrupt(CPUState *cpu); > bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); > +#endif /* !CONFIG_USER_ONLY */ > hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/avr/cpu.c b/target/avr/cpu.c > index ea14175ca55..e9fa54c9777 100644 > --- a/target/avr/cpu.c > +++ b/target/avr/cpu.c > @@ -195,10 +195,10 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D= { > static const struct TCGCPUOps avr_tcg_ops =3D { > .initialize =3D avr_cpu_tcg_init, > .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, > - .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, > .tlb_fill =3D avr_cpu_tlb_fill, > > #ifndef CONFIG_USER_ONLY > + .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, > .do_interrupt =3D avr_cpu_do_interrupt, > #endif /* !CONFIG_USER_ONLY */ > }; > diff --git a/target/avr/helper.c b/target/avr/helper.c > index 981c29da453..84e366d94a3 100644 > --- a/target/avr/helper.c > +++ b/target/avr/helper.c > @@ -25,6 +25,7 @@ > #include "exec/address-spaces.h" > #include "exec/helper-proto.h" > > +#ifndef CONFIG_USER_ONLY > bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > { > bool ret =3D false; > @@ -91,6 +92,7 @@ void avr_cpu_do_interrupt(CPUState *cs) > > cs->exception_index =3D -1; > } > +#endif /* !CONFIG_USER_ONLY */ > > int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, > int len, bool is_write) > -- > 2.31.1 > > --00000000000033378f05cb08dd96 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:18 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/avr/cpu.h=C2=A0 =C2=A0 | 2 ++
=C2=A0target/avr/cpu.c=C2=A0 =C2=A0 | 2 +-
=C2=A0target/avr/helper.c | 2 ++
=C2=A03 files changed, 5 insertions(+), 1 deletion(-)
=
Reviewed-by: Warner Losh <imp@bsdimp.com>
=C2=A0
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 93e3faa0a98..6f8c0ffd770 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -156,8 +156,10 @@ typedef struct AVRCPU {

=C2=A0extern const struct VMStateDescription vms_avr_cpu;

+#ifndef CONFIG_USER_ONLY
=C2=A0void avr_cpu_do_interrupt(CPUState *cpu);
=C2=A0bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
=C2=A0hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
=C2=A0int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= );
=C2=A0int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);=
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index ea14175ca55..e9fa54c9777 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -195,10 +195,10 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D {=
=C2=A0static const struct TCGCPUOps avr_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.initialize =3D avr_cpu_tcg_init,
=C2=A0 =C2=A0 =C2=A0.synchronize_from_tb =3D avr_cpu_synchronize_from_tb, -=C2=A0 =C2=A0 .cpu_exec_interrupt =3D avr_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D avr_cpu_tlb_fill,

=C2=A0#ifndef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D avr_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D avr_cpu_do_interrupt,
=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 981c29da453..84e366d94a3 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -25,6 +25,7 @@
=C2=A0#include "exec/address-spaces.h"
=C2=A0#include "exec/helper-proto.h"

+#ifndef CONFIG_USER_ONLY
=C2=A0bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0bool ret =3D false;
@@ -91,6 +92,7 @@ void avr_cpu_do_interrupt(CPUState *cs)

=C2=A0 =C2=A0 =C2=A0cs->exception_index =3D -1;
=C2=A0}
+#endif /* !CONFIG_USER_ONLY */

=C2=A0int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int len, bool is_write)
--
2.31.1

--00000000000033378f05cb08dd96-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mLtB0-0001Bg-Eu for mharc-qemu-riscv@gnu.org; Thu, 02 Sep 2021 16:19:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40044) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLt8r-00046X-Sh for qemu-riscv@nongnu.org; Thu, 02 Sep 2021 16:16:58 -0400 Received: from mail-ua1-x92d.google.com ([2607:f8b0:4864:20::92d]:36492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLt8p-0007Ix-W4 for qemu-riscv@nongnu.org; Thu, 02 Sep 2021 16:16:57 -0400 Received: by mail-ua1-x92d.google.com with SMTP id x23so1585623uav.3 for ; Thu, 02 Sep 2021 13:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=PPnlERc7u6MmKGlf0skuXfDJNggzkZn3z7puXsTnSGI=; b=gXFelTolWhXcGwOUQ8qd4G5wX34KjIcx/HGCdyzFHXafkuzeX148ceKMgpiDczKY9s a2ki2Z2b5yKfxZWrnBEFsNOk2tMNCIGTuxgJz2E2FouW/iYHTMiyuIlj1CcivGs8AjO5 vz9b23EbkqCDfvEjOdaLATg2kumJADmlW2Xzqvtd5tkh5slougPyKrUneZfrJM1bW6Ge 1K8jLiu7C9HVGbV46SnMby8C7TI+KI5kbBkOx9RG3IZ1xDdiU3T/Txid4m4D18WhMQ00 2dTQ3ZIge8CS3eNu4ZeZQ3jrSSQ7sFdO/vmHLTaeTMxDSUShpkUeFZocZ3KuoqcNJVtY aGCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PPnlERc7u6MmKGlf0skuXfDJNggzkZn3z7puXsTnSGI=; b=MnzcdbP9aP2AqNavS3RgquE1hUC3FpFxtQObsgDG7C8kwhrOao2KK24FRri0TKSjT/ bntb6XyUwjAqgswqcry9MJJLPd68B9x5dNyWYVpmGMLClAOfntsSlJJj17fRQ4wg4Zzn WATtI1bArd4lBDhjHMbiWXhJsu973ccQZ13oyppgQmJ6VRaUORO1ZtTrk1VZ1+n6yRIi PaNFMwppA4lm1Txmz6WrWBW6phczw8op8dLLxApd0XSig5owaM1WAiz52QpUejIhKRBh luCa7Vy4wpoh8ZuKKRBJUzkjv2m+QbdeNcrnamQahd+rnt0DFpkfU4HquWm0LKzCeL0B zhYg== X-Gm-Message-State: AOAM530rgi4QwebDhjcMP/MbEutF7GZ50qE77lvIAFpIDXyXJhlM6DwE jWmoXVxEYrD4z2bhzmd6X2tYMxBRW5pH9rFDoU2lfQ== X-Google-Smtp-Source: ABdhPJynXdHCd8eJG54f42eLbPaOcq95rPiXaffj04QawshNpG98LF9S9cKxHtovEsQOEpoM4iSJy+rjGXJyjS4Cvh4= X-Received: by 2002:ab0:3413:: with SMTP id z19mr59626uap.39.1630613814846; Thu, 02 Sep 2021 13:16:54 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-9-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-9-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:16:44 -0600 Message-ID: Subject: Re: [PATCH 08/24] target/avr: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Yoshinori Sato , Jiaxun Yang , qemu-arm , Palmer Dabbelt , Max Filippov , Michael Rolnik , Stafford Horne , Paolo Bonzini , "Edgar E. Iglesias" , Bin Meng , Chris Wulff , Mark Cave-Ayland , David Gibson , Kyle Evans , Peter Maydell , Aurelien Jarno , Eduardo Habkost , Marek Vasut , Artyom Tarasenko , Aleksandar Rikalo , Greg Kurz , qemu-riscv@nongnu.org, Laurent Vivier , qemu-ppc , Richard Henderson , Alistair Francis Content-Type: multipart/alternative; boundary="00000000000033378f05cb08dd96" Received-SPF: none client-ip=2607:f8b0:4864:20::92d; envelope-from=wlosh@bsdimp.com; helo=mail-ua1-x92d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 02 Sep 2021 16:19:05 -0400 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Sep 2021 20:16:59 -0000 --00000000000033378f05cb08dd96 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/avr/cpu.h | 2 ++ > target/avr/cpu.c | 2 +- > target/avr/helper.c | 2 ++ > 3 files changed, 5 insertions(+), 1 deletion(-) > Reviewed-by: Warner Losh > diff --git a/target/avr/cpu.h b/target/avr/cpu.h > index 93e3faa0a98..6f8c0ffd770 100644 > --- a/target/avr/cpu.h > +++ b/target/avr/cpu.h > @@ -156,8 +156,10 @@ typedef struct AVRCPU { > > extern const struct VMStateDescription vms_avr_cpu; > > +#ifndef CONFIG_USER_ONLY > void avr_cpu_do_interrupt(CPUState *cpu); > bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); > +#endif /* !CONFIG_USER_ONLY */ > hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/avr/cpu.c b/target/avr/cpu.c > index ea14175ca55..e9fa54c9777 100644 > --- a/target/avr/cpu.c > +++ b/target/avr/cpu.c > @@ -195,10 +195,10 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D= { > static const struct TCGCPUOps avr_tcg_ops =3D { > .initialize =3D avr_cpu_tcg_init, > .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, > - .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, > .tlb_fill =3D avr_cpu_tlb_fill, > > #ifndef CONFIG_USER_ONLY > + .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, > .do_interrupt =3D avr_cpu_do_interrupt, > #endif /* !CONFIG_USER_ONLY */ > }; > diff --git a/target/avr/helper.c b/target/avr/helper.c > index 981c29da453..84e366d94a3 100644 > --- a/target/avr/helper.c > +++ b/target/avr/helper.c > @@ -25,6 +25,7 @@ > #include "exec/address-spaces.h" > #include "exec/helper-proto.h" > > +#ifndef CONFIG_USER_ONLY > bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) > { > bool ret =3D false; > @@ -91,6 +92,7 @@ void avr_cpu_do_interrupt(CPUState *cs) > > cs->exception_index =3D -1; > } > +#endif /* !CONFIG_USER_ONLY */ > > int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, > int len, bool is_write) > -- > 2.31.1 > > --00000000000033378f05cb08dd96 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:18 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/avr/cpu.h=C2=A0 =C2=A0 | 2 ++
=C2=A0target/avr/cpu.c=C2=A0 =C2=A0 | 2 +-
=C2=A0target/avr/helper.c | 2 ++
=C2=A03 files changed, 5 insertions(+), 1 deletion(-)
=
Reviewed-by: Warner Losh <imp@bsdimp.com>
=C2=A0
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 93e3faa0a98..6f8c0ffd770 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -156,8 +156,10 @@ typedef struct AVRCPU {

=C2=A0extern const struct VMStateDescription vms_avr_cpu;

+#ifndef CONFIG_USER_ONLY
=C2=A0void avr_cpu_do_interrupt(CPUState *cpu);
=C2=A0bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
=C2=A0hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
=C2=A0int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= );
=C2=A0int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);=
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index ea14175ca55..e9fa54c9777 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -195,10 +195,10 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D {=
=C2=A0static const struct TCGCPUOps avr_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.initialize =3D avr_cpu_tcg_init,
=C2=A0 =C2=A0 =C2=A0.synchronize_from_tb =3D avr_cpu_synchronize_from_tb, -=C2=A0 =C2=A0 .cpu_exec_interrupt =3D avr_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D avr_cpu_tlb_fill,

=C2=A0#ifndef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D avr_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D avr_cpu_do_interrupt,
=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 981c29da453..84e366d94a3 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -25,6 +25,7 @@
=C2=A0#include "exec/address-spaces.h"
=C2=A0#include "exec/helper-proto.h"

+#ifndef CONFIG_USER_ONLY
=C2=A0bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0bool ret =3D false;
@@ -91,6 +92,7 @@ void avr_cpu_do_interrupt(CPUState *cs)

=C2=A0 =C2=A0 =C2=A0cs->exception_index =3D -1;
=C2=A0}
+#endif /* !CONFIG_USER_ONLY */

=C2=A0int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int len, bool is_write)
--
2.31.1

--00000000000033378f05cb08dd96--