From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBA26C433F5 for ; Wed, 15 Sep 2021 16:12:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2E42B60FED for ; Wed, 15 Sep 2021 16:12:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2E42B60FED Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bsdimp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:41654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQXWI-0006tQ-2L for qemu-devel@archiver.kernel.org; Wed, 15 Sep 2021 12:12:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQXTV-0004fl-1g for qemu-devel@nongnu.org; Wed, 15 Sep 2021 12:09:29 -0400 Received: from mail-vs1-xe2d.google.com ([2607:f8b0:4864:20::e2d]:42498) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mQXTP-0002pf-Lj for qemu-devel@nongnu.org; Wed, 15 Sep 2021 12:09:27 -0400 Received: by mail-vs1-xe2d.google.com with SMTP id z62so3242556vsz.9 for ; Wed, 15 Sep 2021 09:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Fm/sy9iM9naqGnP/5sfxV1+QZupq/xphCd5l41V/6CY=; b=VpOniOF/cLbZQmITTM8XiJvpJQJLklyd1yukhFj+NbqtPPFtERpHDhtmF1s7GtIxY3 1YtnV7k699bDnT6RWEjusAn/m0Pwqc4SWy4eDMye3v5fJHqPWyChe2XaZKkyyRkXa+ld QDiHXVicmTOdKV5cndNneVl35N+/3eRUlMxll0nIYkLS1tn2aEYuH8hJhdeo4hmNAYE8 qds43hIC4e2i8Xy/GfFKu9cGhUPHCR//dvM+qeJr5/SSMSNu6ASrt2LUmVnWJhFHn9LL DNWRZjK+3R9tGE/pUpGLtBu99rJTBtlwApAL8FWUciiBjl/hVBqsV8QO8FwoYCn/oBlj TE4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Fm/sy9iM9naqGnP/5sfxV1+QZupq/xphCd5l41V/6CY=; b=y28RvZ5QI+UkGEDAXlo8zqedh+rTCh8jYHZ5srWNy6ll507KXx+Rdg3fX6t6sCqTQY HqkfY9/nfhsuM/rxJvGzH0zqh913Y/FSTcTBjVFetdbYC+mRY0YzIqipYMLzftAYHopN jlZq8Cn/jTKgCWTgMxDSRtd6wtHoS0PFrX6HEBrn0p02tPcVev+GMs9UMTx86C9jvATw l6bGvzibSqr9nJB/00r903hCB5DBYRvsc2V4J/h5B8YxFFSub1hGr1BvIWz0F0XfNosi HHRVIQwkEf0dnQ5teXNnjK9eJGS4YjqVO4YIYAmQP//R45WK7rB+4byxBRD7vT49XqhM jvIQ== X-Gm-Message-State: AOAM533zbcRQapKl8JuGXHuQ0lyJVcdg+0yeGOWWylEkaMqANr/YJCsI OizPmTJ9ZMRItmCXWmLsq7gZH9I8fHYYdJRepAlqug== X-Google-Smtp-Source: ABdhPJyxfFu1R55KLhm/ivbumPC9HJ6X8DEd6oePLUCCwx1wq/On7tLnWyfl48DaY5fb48SfZurxJ+rWv+xojRmt1/Y= X-Received: by 2002:a67:d589:: with SMTP id m9mr429497vsj.30.1631722160905; Wed, 15 Sep 2021 09:09:20 -0700 (PDT) MIME-Version: 1.0 References: <20210913220552.604064-1-richard.henderson@linaro.org> <20210913220552.604064-2-richard.henderson@linaro.org> In-Reply-To: <20210913220552.604064-2-richard.henderson@linaro.org> From: Warner Losh Date: Wed, 15 Sep 2021 10:09:10 -0600 Message-ID: Subject: Re: [RFC PATCH 1/7] include/exec: Move cpu_signal_handler declaration To: Richard Henderson Content-Type: multipart/alternative; boundary="000000000000c5f88505cc0aeb45" Received-SPF: none client-ip=2607:f8b0:4864:20::e2d; envelope-from=wlosh@bsdimp.com; helo=mail-vs1-xe2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , QEMU Developers , Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000c5f88505cc0aeb45 Content-Type: text/plain; charset="UTF-8" On Mon, Sep 13, 2021 at 4:05 PM Richard Henderson < richard.henderson@linaro.org> wrote: > There is nothing target specific about this. The implementation > is host specific, but the declaration is 100% common. > > Reviewed-by: Alistair Francis > Signed-off-by: Richard Henderson > --- > include/exec/exec-all.h | 13 +++++++++++++ > target/alpha/cpu.h | 6 ------ > target/arm/cpu.h | 7 ------- > target/avr/cpu.h | 2 -- > target/cris/cpu.h | 8 -------- > target/hexagon/cpu.h | 3 --- > target/hppa/cpu.h | 3 --- > target/i386/cpu.h | 7 ------- > target/m68k/cpu.h | 8 -------- > target/microblaze/cpu.h | 7 ------- > target/mips/cpu.h | 3 --- > target/mips/internal.h | 2 -- > target/nios2/cpu.h | 2 -- > target/openrisc/cpu.h | 2 -- > target/ppc/cpu.h | 7 ------- > target/riscv/cpu.h | 2 -- > target/rx/cpu.h | 4 ---- > target/s390x/cpu.h | 7 ------- > target/sh4/cpu.h | 3 --- > target/sparc/cpu.h | 2 -- > target/tricore/cpu.h | 2 -- > target/xtensa/cpu.h | 2 -- > 22 files changed, 13 insertions(+), 89 deletions(-) > Reviewed-By: Warner Losh Warner > diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h > index 5d1b6d80fb..9d5987ba04 100644 > --- a/include/exec/exec-all.h > +++ b/include/exec/exec-all.h > @@ -662,6 +662,19 @@ static inline tb_page_addr_t > get_page_addr_code_hostp(CPUArchState *env, > } > return addr; > } > + > +/** > + * cpu_signal_handler > + * @signum: host signal number > + * @pinfo: host siginfo_t > + * @puc: host ucontext_t > + * > + * To be called from the SIGBUS and SIGSEGV signal handler to inform the > + * virtual cpu of exceptions. Returns true if the signal was handled by > + * the virtual CPU. > + */ > +int cpu_signal_handler(int signum, void *pinfo, void *puc); > + > #else > static inline void mmap_lock(void) {} > static inline void mmap_unlock(void) {} > diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h > index 4e993bd15b..ce9ec32199 100644 > --- a/target/alpha/cpu.h > +++ b/target/alpha/cpu.h > @@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, > vaddr addr, > int mmu_idx, uintptr_t retaddr); > > #define cpu_list alpha_cpu_list > -#define cpu_signal_handler cpu_alpha_signal_handler > > typedef CPUAlphaState CPUArchState; > typedef AlphaCPU ArchCPU; > @@ -440,11 +439,6 @@ void alpha_translate_init(void); > #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU > > void alpha_cpu_list(void); > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_alpha_signal_handler(int host_signum, void *pinfo, > - void *puc); > bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index cfd755cff9..6c78957e54 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env) > return env->aarch64; > } > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_arm_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > /** > * pmu_op_start/finish > * @env: CPUARMState > @@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool > kvm_sync); > #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_ARM_CPU > > -#define cpu_signal_handler cpu_arm_signal_handler > #define cpu_list arm_cpu_list > > /* ARM has the following "translation regimes" (as the ARM ARM calls > them): > diff --git a/target/avr/cpu.h b/target/avr/cpu.h > index 93e3faa0a9..dceacf3cd7 100644 > --- a/target/avr/cpu.h > +++ b/target/avr/cpu.h > @@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, > int feature) > } > > #define cpu_list avr_cpu_list > -#define cpu_signal_handler cpu_avr_signal_handler > #define cpu_mmu_index avr_cpu_mmu_index > > static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) > @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void); > > void avr_cpu_list(void); > int cpu_avr_exec(CPUState *cpu); > -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); > int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, > int len, bool is_write); > > diff --git a/target/cris/cpu.h b/target/cris/cpu.h > index be021899ae..6603565f83 100644 > --- a/target/cris/cpu.h > +++ b/target/cris/cpu.h > @@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, > GByteArray *buf, int reg); > int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_cris_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > void cris_initialize_tcg(void); > void cris_initialize_crisv10_tcg(void); > > @@ -250,8 +244,6 @@ enum { > #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU > > -#define cpu_signal_handler cpu_cris_signal_handler > - > /* MMU modes definitions */ > #define MMU_USER_IDX 1 > static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) > diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h > index 2855dd3881..f7d043865b 100644 > --- a/target/hexagon/cpu.h > +++ b/target/hexagon/cpu.h > @@ -129,9 +129,6 @@ typedef struct HexagonCPU { > > #include "cpu_bits.h" > > -#define cpu_signal_handler cpu_hexagon_signal_handler > -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); > - > static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, > target_ulong *pc, > target_ulong *cs_base, uint32_t > *flags) > { > diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h > index 7854675b90..d3cb7a279f 100644 > --- a/target/hppa/cpu.h > +++ b/target/hppa/cpu.h > @@ -319,9 +319,6 @@ static inline void > cpu_hppa_change_prot_id(CPUHPPAState *env) { } > void cpu_hppa_change_prot_id(CPUHPPAState *env); > #endif > > -#define cpu_signal_handler cpu_hppa_signal_handler > - > -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); > hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); > int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 7dd664791a..c2954c71ea 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong > ptr, int data32); > void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); > void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_x86_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > /* cpu.c */ > void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, > uint32_t vendor2, uint32_t vendor3); > @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); > #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") > #endif > > -#define cpu_signal_handler cpu_x86_signal_handler > #define cpu_list x86_cpu_list > > /* MMU modes definitions */ > diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h > index 550eb028b6..a3423729ef 100644 > --- a/target/m68k/cpu.h > +++ b/target/m68k/cpu.h > @@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, > uint8_t *buf, int reg); > > void m68k_tcg_init(void); > void m68k_cpu_init_gdb(M68kCPU *cpu); > -/* > - * you can call this signal handler from your SIGBUS and SIGSEGV > - * signal handlers to inform the virtual CPU of exceptions. non zero > - * is returned if the signal was handled by the virtual CPU. > - */ > -int cpu_m68k_signal_handler(int host_signum, void *pinfo, > - void *puc); > uint32_t cpu_m68k_get_ccr(CPUM68KState *env); > void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); > void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); > @@ -563,7 +556,6 @@ enum { > #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_M68K_CPU > > -#define cpu_signal_handler cpu_m68k_signal_handler > #define cpu_list m68k_cpu_list > > /* MMU modes definitions */ > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 40401c33b7..13ed3cd4dd 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, > uint32_t val) > } > > void mb_tcg_init(void); > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_mb_signal_handler(int host_signum, void *pinfo, > - void *puc); > > #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU > > -#define cpu_signal_handler cpu_mb_signal_handler > - > /* MMU modes definitions */ > #define MMU_NOMMU_IDX 0 > #define MMU_KERNEL_IDX 1 > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index 1dfe69c6c0..56b1cbd091 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -1193,7 +1193,6 @@ struct MIPSCPU { > > void mips_cpu_list(void); > > -#define cpu_signal_handler cpu_mips_signal_handler > #define cpu_list mips_cpu_list > > extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); > @@ -1277,8 +1276,6 @@ enum { > */ > #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 > > -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); > - > #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU > #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU > diff --git a/target/mips/internal.h b/target/mips/internal.h > index eecdd10116..daddb05fd4 100644 > --- a/target/mips/internal.h > +++ b/target/mips/internal.h > @@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu; > > #endif /* !CONFIG_USER_ONLY */ > > -#define cpu_signal_handler cpu_mips_signal_handler > - > static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) > { > return (env->CP0_Status & (1 << CP0St_IE)) && > diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h > index 2ab82fdc71..88a511209c 100644 > --- a/target/nios2/cpu.h > +++ b/target/nios2/cpu.h > @@ -193,7 +193,6 @@ struct Nios2CPU { > > void nios2_tcg_init(void); > void nios2_cpu_do_interrupt(CPUState *cs); > -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); > void dump_mmu(CPUNios2State *env); > void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); > hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > @@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env); > #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU > > #define cpu_gen_code cpu_nios2_gen_code > -#define cpu_signal_handler cpu_nios2_signal_handler > > #define CPU_SAVE_VERSION 1 > > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index be6df81a81..187a4a114e 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -320,11 +320,9 @@ void openrisc_translate_init(void); > bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); > int print_insn_or1k(bfd_vma addr, disassemble_info *info); > > #define cpu_list cpu_openrisc_list > -#define cpu_signal_handler cpu_openrisc_signal_handler > > #ifndef CONFIG_USER_ONLY > extern const VMStateDescription vmstate_openrisc_cpu; > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 362e7c4c5c..01d3773bc7 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu; > > > /*****************************************************************************/ > void ppc_translate_init(void); > -/* > - * you can call this signal handler from your SIGBUS and SIGSEGV > - * signal handlers to inform the virtual CPU of exceptions. non zero > - * is returned if the signal was handled by the virtual CPU. > - */ > -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); > bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > @@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, > uint32_t val); > #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU > > -#define cpu_signal_handler cpu_ppc_signal_handler > #define cpu_list ppc_cpu_list > > /* MMU modes definitions */ > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e735e53e26..465142616a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, > hwaddr physaddr, > char *riscv_isa_string(RISCVCPU *cpu); > void riscv_cpu_list(void); > > -#define cpu_signal_handler riscv_cpu_signal_handler > #define cpu_list riscv_cpu_list > #define cpu_mmu_index riscv_cpu_mmu_index > > @@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, > uint64_t (*fn)(uint32_t), > void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); > > void riscv_translate_init(void); > -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); > void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, > uint32_t exception, uintptr_t > pc); > > diff --git a/target/rx/cpu.h b/target/rx/cpu.h > index faa3606f52..4ac71aec37 100644 > --- a/target/rx/cpu.h > +++ b/target/rx/cpu.h > @@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t > *buf, int reg); > hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > > void rx_translate_init(void); > -int cpu_rx_signal_handler(int host_signum, void *pinfo, > - void *puc); > - > void rx_cpu_list(void); > void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); > > -#define cpu_signal_handler cpu_rx_signal_handler > #define cpu_list rx_cpu_list > > #include "exec/cpu-all.h" > diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h > index b26ae8fff2..3153d053e9 100644 > --- a/target/s390x/cpu.h > +++ b/target/s390x/cpu.h > @@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t > gen, uint8_t ec_ga, > #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_S390_CPU > > -/* you can call this signal handler from your SIGBUS and SIGSEGV > - signal handlers to inform the virtual CPU of exceptions. non zero > - is returned if the signal was handled by the virtual CPU. */ > -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); > -#define cpu_signal_handler cpu_s390x_signal_handler > - > - > /* interrupt.c */ > #define RA_IGNORED 0 > void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t > ra); > diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h > index 017a770214..56f7c32df9 100644 > --- a/target/sh4/cpu.h > +++ b/target/sh4/cpu.h > @@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, > vaddr addr, > int mmu_idx, uintptr_t retaddr); > > void sh4_translate_init(void); > -int cpu_sh4_signal_handler(int host_signum, void *pinfo, > - void *puc); > bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > @@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env); > #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU > > -#define cpu_signal_handler cpu_sh4_signal_handler > #define cpu_list sh4_cpu_list > > /* MMU modes definitions */ > diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h > index ff8ae73002..6b40d02237 100644 > --- a/target/sparc/cpu.h > +++ b/target/sparc/cpu.h > @@ -649,13 +649,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, > target_ulong addr, > int mmu_idx); > #endif > #endif > -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); > > #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU > #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX > #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU > > -#define cpu_signal_handler cpu_sparc_signal_handler > #define cpu_list sparc_cpu_list > > /* MMU modes definitions */ > diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h > index 4b61a2c03f..c461387e71 100644 > --- a/target/tricore/cpu.h > +++ b/target/tricore/cpu.h > @@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env); > > void tricore_cpu_list(void); > > -#define cpu_signal_handler cpu_tricore_signal_handler > #define cpu_list tricore_cpu_list > > static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) > @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU; > > void cpu_state_reset(CPUTriCoreState *s); > void tricore_tcg_init(void); > -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); > > static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, > target_ulong *pc, > target_ulong *cs_base, uint32_t > *flags) > diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h > index cbb720e7cc..646965f379 100644 > --- a/target/xtensa/cpu.h > +++ b/target/xtensa/cpu.h > @@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, > vaddr addr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > > -#define cpu_signal_handler cpu_xtensa_signal_handler > #define cpu_list xtensa_cpu_list > > #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU > @@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s); > void xtensa_irq_init(CPUXtensaState *env); > qemu_irq *xtensa_get_extints(CPUXtensaState *env); > qemu_irq xtensa_get_runstall(CPUXtensaState *env); > -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); > void xtensa_cpu_list(void); > void xtensa_sync_window_from_phys(CPUXtensaState *env); > void xtensa_sync_phys_from_window(CPUXtensaState *env); > -- > 2.25.1 > > --000000000000c5f88505cc0aeb45 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Mon, Sep 13, 2021 at 4:05 PM Richa= rd Henderson <richard.he= nderson@linaro.org> wrote:
There is nothing target specific about this.=C2=A0 The im= plementation
is host specific, but the declaration is 100% common.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
=C2=A0include/exec/exec-all.h | 13 +++++++++++++
=C2=A0target/alpha/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 6 ------
=C2=A0target/arm/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 7 -------
=C2=A0target/avr/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 --
=C2=A0target/cris/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 8 --------
=C2=A0target/hexagon/cpu.h=C2=A0 =C2=A0 |=C2=A0 3 ---
=C2=A0target/hppa/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 3 ---
=C2=A0target/i386/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 7 -------
=C2=A0target/m68k/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 8 --------
=C2=A0target/microblaze/cpu.h |=C2=A0 7 -------
=C2=A0target/mips/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 3 ---
=C2=A0target/mips/internal.h=C2=A0 |=C2=A0 2 --
=C2=A0target/nios2/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 --
=C2=A0target/openrisc/cpu.h=C2=A0 =C2=A0|=C2=A0 2 --
=C2=A0target/ppc/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 7 -------
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 --
=C2=A0target/rx/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 4 ----
=C2=A0target/s390x/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 7 -------
=C2=A0target/sh4/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 3 ---
=C2=A0target/sparc/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 --
=C2=A0target/tricore/cpu.h=C2=A0 =C2=A0 |=C2=A0 2 --
=C2=A0target/xtensa/cpu.h=C2=A0 =C2=A0 =C2=A0|=C2=A0 2 --
=C2=A022 files changed, 13 insertions(+), 89 deletions(-)
<= div>
Reviewed-By: Warner Losh <imp@bsdimp.com>

Warner
=C2= =A0
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 5d1b6d80fb..9d5987ba04 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -662,6 +662,19 @@ static inline tb_page_addr_t get_page_addr_code_hostp(= CPUArchState *env,
=C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0return addr;
=C2=A0}
+
+/**
+ * cpu_signal_handler
+ * @signum: host signal number
+ * @pinfo: host siginfo_t
+ * @puc: host ucontext_t
+ *
+ * To be called from the SIGBUS and SIGSEGV signal handler to inform the + * virtual cpu of exceptions.=C2=A0 Returns true if the signal was handled= by
+ * the virtual CPU.
+ */
+int cpu_signal_handler(int signum, void *pinfo, void *puc);
+
=C2=A0#else
=C2=A0static inline void mmap_lock(void) {}
=C2=A0static inline void mmap_unlock(void) {}
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 4e993bd15b..ce9ec32199 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -287,7 +287,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int mmu_idx, uintptr_t= retaddr);

=C2=A0#define cpu_list alpha_cpu_list
-#define cpu_signal_handler cpu_alpha_signal_handler

=C2=A0typedef CPUAlphaState CPUArchState;
=C2=A0typedef AlphaCPU ArchCPU;
@@ -440,11 +439,6 @@ void alpha_translate_init(void);
=C2=A0#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU

=C2=A0void alpha_cpu_list(void);
-/* you can call this signal handler from your SIGBUS and SIGSEGV
-=C2=A0 =C2=A0signal handlers to inform the virtual CPU of exceptions. non = zero
-=C2=A0 =C2=A0is returned if the signal was handled by the virtual CPU.=C2= =A0 */
-int cpu_alpha_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *puc);
=C2=A0bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0MMUAccessType access_type, int mmu_idx,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0bool probe, uintptr_t retaddr);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cfd755cff9..6c78957e54 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1121,12 +1121,6 @@ static inline bool is_a64(CPUARMState *env)
=C2=A0 =C2=A0 =C2=A0return env->aarch64;
=C2=A0}

-/* you can call this signal handler from your SIGBUS and SIGSEGV
-=C2=A0 =C2=A0signal handlers to inform the virtual CPU of exceptions. non = zero
-=C2=A0 =C2=A0is returned if the signal was handled by the virtual CPU.=C2= =A0 */
-int cpu_arm_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0void *puc);
-
=C2=A0/**
=C2=A0 * pmu_op_start/finish
=C2=A0 * @env: CPUARMState
@@ -3015,7 +3009,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c);
=C2=A0#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
=C2=A0#define CPU_RESOLVING_TYPE TYPE_ARM_CPU

-#define cpu_signal_handler cpu_arm_signal_handler
=C2=A0#define cpu_list arm_cpu_list

=C2=A0/* ARM has the following "translation regimes" (as the ARM = ARM calls them):
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 93e3faa0a9..dceacf3cd7 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -175,7 +175,6 @@ static inline void set_avr_feature(CPUAVRState *env, in= t feature)
=C2=A0}

=C2=A0#define cpu_list avr_cpu_list
-#define cpu_signal_handler cpu_avr_signal_handler
=C2=A0#define cpu_mmu_index avr_cpu_mmu_index

=C2=A0static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) @@ -187,7 +186,6 @@ void avr_cpu_tcg_init(void);

=C2=A0void avr_cpu_list(void);
=C2=A0int cpu_avr_exec(CPUState *cpu);
-int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc);
=C2=A0int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf= ,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int len, bool is_write);

diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index be021899ae..6603565f83 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -199,12 +199,6 @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByte= Array *buf, int reg);
=C2=A0int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int re= g);
=C2=A0int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)= ;

-/* you can call this signal handler from your SIGBUS and SIGSEGV
-=C2=A0 =C2=A0signal handlers to inform the virtual CPU of exceptions. non = zero
-=C2=A0 =C2=A0is returned if the signal was handled by the virtual CPU.=C2= =A0 */
-int cpu_cris_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0void *puc);
-
=C2=A0void cris_initialize_tcg(void);
=C2=A0void cris_initialize_crisv10_tcg(void);

@@ -250,8 +244,6 @@ enum {
=C2=A0#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
=C2=A0#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU

-#define cpu_signal_handler cpu_cris_signal_handler
-
=C2=A0/* MMU modes definitions */
=C2=A0#define MMU_USER_IDX 1
=C2=A0static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 2855dd3881..f7d043865b 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -129,9 +129,6 @@ typedef struct HexagonCPU {

=C2=A0#include "cpu_bits.h"

-#define cpu_signal_handler cpu_hexagon_signal_handler
-int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); -
=C2=A0static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_= ulong *pc,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ta= rget_ulong *cs_base, uint32_t *flags)
=C2=A0{
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 7854675b90..d3cb7a279f 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -319,9 +319,6 @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState= *env) { }
=C2=A0void cpu_hppa_change_prot_id(CPUHPPAState *env);
=C2=A0#endif

-#define cpu_signal_handler cpu_hppa_signal_handler
-
-int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);
=C2=A0hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
=C2=A0int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int re= g);
=C2=A0int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)= ;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7dd664791a..c2954c71ea 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1947,12 +1947,6 @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr= , int data32);
=C2=A0void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
=C2=A0void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);

-/* you can call this signal handler from your SIGBUS and SIGSEGV
-=C2=A0 =C2=A0signal handlers to inform the virtual CPU of exceptions. non = zero
-=C2=A0 =C2=A0is returned if the signal was handled by the virtual CPU.=C2= =A0 */
-int cpu_x86_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0void *puc);
-
=C2=A0/* cpu.c */
=C2=A0void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t vendor2, uint32_t vendor3);<= br> @@ -2020,7 +2014,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
=C2=A0#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")=
=C2=A0#endif

-#define cpu_signal_handler cpu_x86_signal_handler
=C2=A0#define cpu_list x86_cpu_list

=C2=A0/* MMU modes definitions */
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 550eb028b6..a3423729ef 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -177,13 +177,6 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg);

=C2=A0void m68k_tcg_init(void);
=C2=A0void m68k_cpu_init_gdb(M68kCPU *cpu);
-/*
- * you can call this signal handler from your SIGBUS and SIGSEGV
- * signal handlers to inform the virtual CPU of exceptions. non zero
- * is returned if the signal was handled by the virtual CPU.
- */
-int cpu_m68k_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0void *puc);
=C2=A0uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
=C2=A0void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
=C2=A0void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
@@ -563,7 +556,6 @@ enum {
=C2=A0#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
=C2=A0#define CPU_RESOLVING_TYPE TYPE_M68K_CPU

-#define cpu_signal_handler cpu_m68k_signal_handler
=C2=A0#define cpu_list m68k_cpu_list

=C2=A0/* MMU modes definitions */
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 40401c33b7..13ed3cd4dd 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -385,16 +385,9 @@ static inline void mb_cpu_write_msr(CPUMBState *env, u= int32_t val)
=C2=A0}

=C2=A0void mb_tcg_init(void);
-/* you can call this signal handler from your SIGBUS and SIGSEGV
-=C2=A0 =C2=A0signal handlers to inform the virtual CPU of exceptions. non = zero
-=C2=A0 =C2=A0is returned if the signal was handled by the virtual CPU.=C2= =A0 */
-int cpu_mb_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 void *puc);

=C2=A0#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU

-#define cpu_signal_handler cpu_mb_signal_handler
-
=C2=A0/* MMU modes definitions */
=C2=A0#define MMU_NOMMU_IDX=C2=A0 =C2=A00
=C2=A0#define MMU_KERNEL_IDX=C2=A0 1
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1dfe69c6c0..56b1cbd091 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1193,7 +1193,6 @@ struct MIPSCPU {

=C2=A0void mips_cpu_list(void);

-#define cpu_signal_handler cpu_mips_signal_handler
=C2=A0#define cpu_list mips_cpu_list

=C2=A0extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *e= nv);
@@ -1277,8 +1276,6 @@ enum {
=C2=A0 */
=C2=A0#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0

-int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
-
=C2=A0#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
=C2=A0#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
=C2=A0#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
diff --git a/target/mips/internal.h b/target/mips/internal.h
index eecdd10116..daddb05fd4 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -156,8 +156,6 @@ extern const VMStateDescription vmstate_mips_cpu;

=C2=A0#endif /* !CONFIG_USER_ONLY */

-#define cpu_signal_handler cpu_mips_signal_handler
-
=C2=A0static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)<= br> =C2=A0{
=C2=A0 =C2=A0 =C2=A0return (env->CP0_Status & (1 << CP0St_IE))= &&
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ab82fdc71..88a511209c 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -193,7 +193,6 @@ struct Nios2CPU {

=C2=A0void nios2_tcg_init(void);
=C2=A0void nios2_cpu_do_interrupt(CPUState *cs);
-int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc);
=C2=A0void dump_mmu(CPUNios2State *env);
=C2=A0void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
=C2=A0hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
@@ -206,7 +205,6 @@ void do_nios2_semihosting(CPUNios2State *env);
=C2=A0#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU

=C2=A0#define cpu_gen_code cpu_nios2_gen_code
-#define cpu_signal_handler cpu_nios2_signal_handler

=C2=A0#define CPU_SAVE_VERSION 1

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index be6df81a81..187a4a114e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -320,11 +320,9 @@ void openrisc_translate_init(void);
=C2=A0bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 MMUAccessType access_type, int mmu_idx,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 bool probe, uintptr_t retaddr);
-int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);<= br> =C2=A0int print_insn_or1k(bfd_vma addr, disassemble_info *info);

=C2=A0#define cpu_list cpu_openrisc_list
-#define cpu_signal_handler cpu_openrisc_signal_handler

=C2=A0#ifndef CONFIG_USER_ONLY
=C2=A0extern const VMStateDescription vmstate_openrisc_cpu;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 362e7c4c5c..01d3773bc7 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1278,12 +1278,6 @@ extern const VMStateDescription vmstate_ppc_cpu;

=C2=A0/********************************************************************= *********/
=C2=A0void ppc_translate_init(void);
-/*
- * you can call this signal handler from your SIGBUS and SIGSEGV
- * signal handlers to inform the virtual CPU of exceptions. non zero
- * is returned if the signal was handled by the virtual CPU.
- */
-int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
=C2=A0bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0MMUAccessType access_type, int mmu_idx,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0bool probe, uintptr_t retaddr);
@@ -1371,7 +1365,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint3= 2_t val);
=C2=A0#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX =C2=A0#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU

-#define cpu_signal_handler cpu_ppc_signal_handler
=C2=A0#define cpu_list ppc_cpu_list

=C2=A0/* MMU modes definitions */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e735e53e26..465142616a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -356,7 +356,6 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr,
=C2=A0char *riscv_isa_string(RISCVCPU *cpu);
=C2=A0void riscv_cpu_list(void);

-#define cpu_signal_handler riscv_cpu_signal_handler
=C2=A0#define cpu_list riscv_cpu_list
=C2=A0#define cpu_mmu_index riscv_cpu_mmu_index

@@ -372,7 +371,6 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64= _t (*fn)(uint32_t),
=C2=A0void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
=C2=A0void riscv_translate_init(void);
-int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
=C2=A0void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 u= int32_t exception, uintptr_t pc);

diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index faa3606f52..4ac71aec37 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -134,13 +134,9 @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *= buf, int reg);
=C2=A0hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

=C2=A0void rx_translate_init(void);
-int cpu_rx_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0void *puc);
-
=C2=A0void rx_cpu_list(void);
=C2=A0void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);

-#define cpu_signal_handler cpu_rx_signal_handler
=C2=A0#define cpu_list rx_cpu_list

=C2=A0#include "exec/cpu-all.h"
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index b26ae8fff2..3153d053e9 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -809,13 +809,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t ge= n, uint8_t ec_ga,
=C2=A0#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
=C2=A0#define CPU_RESOLVING_TYPE TYPE_S390_CPU

-/* you can call this signal handler from your SIGBUS and SIGSEGV
-=C2=A0 =C2=A0signal handlers to inform the virtual CPU of exceptions. non = zero
-=C2=A0 =C2=A0is returned if the signal was handled by the virtual CPU.=C2= =A0 */
-int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
-#define cpu_signal_handler cpu_s390x_signal_handler
-
-
=C2=A0/* interrupt.c */
=C2=A0#define RA_IGNORED=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 0
=C2=A0void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintpt= r_t ra);
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 017a770214..56f7c32df9 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -213,8 +213,6 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int mmu_idx, uin= tptr_t retaddr);

=C2=A0void sh4_translate_init(void);
-int cpu_sh4_signal_handler(int host_signum, void *pinfo,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0void *puc);
=C2=A0bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 MMUAccessType access_type, int mmu_idx,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 bool probe, uintptr_t retaddr);
@@ -250,7 +248,6 @@ void cpu_load_tlb(CPUSH4State * env);
=C2=A0#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
=C2=A0#define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU

-#define cpu_signal_handler cpu_sh4_signal_handler
=C2=A0#define cpu_list sh4_cpu_list

=C2=A0/* MMU modes definitions */
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index ff8ae73002..6b40d02237 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -649,13 +649,11 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, = target_ulong addr,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 int mmu_idx);
=C2=A0#endif
=C2=A0#endif
-int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

=C2=A0#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
=C2=A0#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
=C2=A0#define CPU_RESOLVING_TYPE TYPE_SPARC_CPU

-#define cpu_signal_handler cpu_sparc_signal_handler
=C2=A0#define cpu_list sparc_cpu_list

=C2=A0/* MMU modes definitions */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 4b61a2c03f..c461387e71 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -362,7 +362,6 @@ void fpu_set_state(CPUTriCoreState *env);

=C2=A0void tricore_cpu_list(void);

-#define cpu_signal_handler cpu_tricore_signal_handler
=C2=A0#define cpu_list tricore_cpu_list

=C2=A0static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) @@ -377,7 +376,6 @@ typedef TriCoreCPU ArchCPU;

=C2=A0void cpu_state_reset(CPUTriCoreState *s);
=C2=A0void tricore_tcg_init(void);
-int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
=C2=A0static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_= ulong *pc,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ta= rget_ulong *cs_base, uint32_t *flags)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index cbb720e7cc..646965f379 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -584,7 +584,6 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vadd= r addr,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MMUAccessType ac= cess_type,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int mmu_idx, uin= tptr_t retaddr);

-#define cpu_signal_handler cpu_xtensa_signal_handler
=C2=A0#define cpu_list xtensa_cpu_list

=C2=A0#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
@@ -613,7 +612,6 @@ void check_interrupts(CPUXtensaState *s);
=C2=A0void xtensa_irq_init(CPUXtensaState *env);
=C2=A0qemu_irq *xtensa_get_extints(CPUXtensaState *env);
=C2=A0qemu_irq xtensa_get_runstall(CPUXtensaState *env);
-int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); =C2=A0void xtensa_cpu_list(void);
=C2=A0void xtensa_sync_window_from_phys(CPUXtensaState *env);
=C2=A0void xtensa_sync_phys_from_window(CPUXtensaState *env);
--
2.25.1

--000000000000c5f88505cc0aeb45--