From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83A93C433F5 for ; Thu, 2 Sep 2021 20:34:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D60F560F11 for ; Thu, 2 Sep 2021 20:34:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D60F560F11 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bsdimp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:44728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLtQI-0004Q0-2Z for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 16:34:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLtIG-0006Wj-Sg for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:26:41 -0400 Received: from mail-vs1-xe2e.google.com ([2607:f8b0:4864:20::e2e]:38884) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLtID-000701-VH for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:26:40 -0400 Received: by mail-vs1-xe2e.google.com with SMTP id a25so2629001vso.5 for ; Thu, 02 Sep 2021 13:26:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cATzV+cgXA9fNf6+6osb5t9LIw0lqjY+rzeij2NRDf0=; b=DRVhSzZsPNOUVAwAQdU3ZfJkRqxYT5ooUQ0xzAZbyEd5BK+RK8v4wCu1oazuQetzeR xCsnZ3/Tn/Q1qs6Y6RjEN2j+Inu7kXf5lvv3ecHK3eluC3dclp8eTrdoWZUD1ZZ5HY3q mgLX0DoKZIp6IaFpDB2MuNMeVpUBIYPQseC7MZpACC/GQO7xt/SyPOAkBlcD5Y1dkfDS sMLRJes9UD7G88UbrMPPUp+h2GNHDHARzwGxHboygmkVk34LRMsZhM33VWYmiKT9rJgB Fe0R3FCb71AJcJZyu90zwFG+cCNzsRKj9/dMNgORreiL6Ske6HZOfYtqG/K0kFnvkzq/ bp/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cATzV+cgXA9fNf6+6osb5t9LIw0lqjY+rzeij2NRDf0=; b=ZpekGeI/ryQIgSuOHveoV14QXLH1ACpkrlH+lf5gzDnFu+wzwhlvrbn+17Y5TxPF/A YnQFfZ7aWxwC9nHyTe3RKz+Aa94yLVAraPQNqTFeOW+ZXCo6DtfkvqVLRocEBlVTIV6n eeVtAHiSgNIAvJOXlMEGp9aX+HyrEwC2P2LRrjGPrSiwiVtZUnSkVbsfPYkKzfpN67sb zjhsLRap+3IpRy3mBE9HkcjMbZK32O7WO9cGQu52hURAhjXHT6RkKkwJPU6Bl88o/zoH 9jVJ5OoOCAOTsiocJTk6uvwLUpvrwqPqHldPpjIjVXzx7N107AnLF1N53s0Tat+pRmNN Cpfg== X-Gm-Message-State: AOAM530/+RCdrqotYHIbKCiHO/2CPGllIqB4ZzNiDlgy/5wfn5tEoKP2 eOBhVSj2tNYmkAtaM/Gyz2SIaK68zSQPA/PJbf074Qtm49i5yij9 X-Google-Smtp-Source: ABdhPJzCQnrZJVyyLjW6ViZm56nxlRoiIb9JOyCCs4FBdQe8rdlDPfVruz1UYu6Sr4ILLM1CDWpjyMkVVqOuUH+hdpo= X-Received: by 2002:a67:2dc6:: with SMTP id t189mr3914121vst.49.1630614396994; Thu, 02 Sep 2021 13:26:36 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-22-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-22-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:26:26 -0600 Message-ID: Subject: Re: [PATCH 21/24] target/rx: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="000000000000e61b4605cb08ff52" Received-SPF: none client-ip=2607:f8b0:4864:20::e2e; envelope-from=wlosh@bsdimp.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bin Meng , Mark Cave-Ayland , QEMU Developers , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , qemu-ppc , Artyom Tarasenko , Aleksandar Rikalo , Eduardo Habkost , Kyle Evans , Richard Henderson , Greg Kurz , qemu-arm , Michael Rolnik , Stafford Horne , David Gibson , qemu-riscv@nongnu.org, Chris Wulff , Laurent Vivier , Palmer Dabbelt , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000e61b4605cb08ff52 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:19 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/rx/cpu.h | 2 ++ > target/rx/cpu.c | 2 +- > target/rx/helper.c | 4 ++++ > 3 files changed, 7 insertions(+), 1 deletion(-) > Reviewed-by: Warner Losh > diff --git a/target/rx/cpu.h b/target/rx/cpu.h > index 0b4b998c7be..faa3606f52f 100644 > --- a/target/rx/cpu.h > +++ b/target/rx/cpu.h > @@ -124,8 +124,10 @@ typedef RXCPU ArchCPU; > #define CPU_RESOLVING_TYPE TYPE_RX_CPU > > const char *rx_crname(uint8_t cr); > +#ifndef CONFIG_USER_ONLY > void rx_cpu_do_interrupt(CPUState *cpu); > bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); > +#endif /* !CONFIG_USER_ONLY */ > void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); > int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/rx/cpu.c b/target/rx/cpu.c > index 96cc96e514f..25a4aa2976d 100644 > --- a/target/rx/cpu.c > +++ b/target/rx/cpu.c > @@ -186,10 +186,10 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D = { > static const struct TCGCPUOps rx_tcg_ops =3D { > .initialize =3D rx_translate_init, > .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, > - .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, > .tlb_fill =3D rx_cpu_tlb_fill, > > #ifndef CONFIG_USER_ONLY > + .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, > .do_interrupt =3D rx_cpu_do_interrupt, > #endif /* !CONFIG_USER_ONLY */ > }; > diff --git a/target/rx/helper.c b/target/rx/helper.c > index db6b07e3890..f34945e7e2c 100644 > --- a/target/rx/helper.c > +++ b/target/rx/helper.c > @@ -40,6 +40,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, > int rte) > env->psw_c =3D FIELD_EX32(psw, PSW, C); > } > > +#ifndef CONFIG_USER_ONLY > + > #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) > void rx_cpu_do_interrupt(CPUState *cs) > { > @@ -142,6 +144,8 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int > interrupt_request) > return false; > } > > +#endif /* !CONFIG_USER_ONLY */ > + > hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > { > return addr; > -- > 2.31.1 > > --000000000000e61b4605cb08ff52 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:19 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/rx/cpu.h=C2=A0 =C2=A0 | 2 ++
=C2=A0target/rx/cpu.c=C2=A0 =C2=A0 | 2 +-
=C2=A0target/rx/helper.c | 4 ++++
=C2=A03 files changed, 7 insertions(+), 1 deletion(-)
=
Reviewed-by: Warner Losh <imp@bsdimp.com>

=C2=A0
=
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..faa3606f52f 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -124,8 +124,10 @@ typedef RXCPU ArchCPU;
=C2=A0#define CPU_RESOLVING_TYPE TYPE_RX_CPU

=C2=A0const char *rx_crname(uint8_t cr);
+#ifndef CONFIG_USER_ONLY
=C2=A0void rx_cpu_do_interrupt(CPUState *cpu);
=C2=A0bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
=C2=A0void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
=C2=A0int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)= ;
=C2=A0int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);<= br> diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 96cc96e514f..25a4aa2976d 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -186,10 +186,10 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D {<= br> =C2=A0static const struct TCGCPUOps rx_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.initialize =3D rx_translate_init,
=C2=A0 =C2=A0 =C2=A0.synchronize_from_tb =3D rx_cpu_synchronize_from_tb, -=C2=A0 =C2=A0 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D rx_cpu_tlb_fill,

=C2=A0#ifndef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D rx_cpu_do_interrupt,
=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
diff --git a/target/rx/helper.c b/target/rx/helper.c
index db6b07e3890..f34945e7e2c 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -40,6 +40,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int= rte)
=C2=A0 =C2=A0 =C2=A0env->psw_c =3D FIELD_EX32(psw, PSW, C);
=C2=A0}

+#ifndef CONFIG_USER_ONLY
+
=C2=A0#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
=C2=A0void rx_cpu_do_interrupt(CPUState *cs)
=C2=A0{
@@ -142,6 +144,8 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_= request)
=C2=A0 =C2=A0 =C2=A0return false;
=C2=A0}

+#endif /* !CONFIG_USER_ONLY */
+
=C2=A0hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0return addr;
--
2.31.1

--000000000000e61b4605cb08ff52-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mLtIH-0006Xx-Sd for mharc-qemu-riscv@gnu.org; Thu, 02 Sep 2021 16:26:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42316) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLtIG-0006Ui-7H for qemu-riscv@nongnu.org; Thu, 02 Sep 2021 16:26:40 -0400 Received: from mail-vs1-xe31.google.com ([2607:f8b0:4864:20::e31]:45997) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLtIE-000705-19 for qemu-riscv@nongnu.org; Thu, 02 Sep 2021 16:26:39 -0400 Received: by mail-vs1-xe31.google.com with SMTP id a21so2623560vsp.12 for ; Thu, 02 Sep 2021 13:26:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cATzV+cgXA9fNf6+6osb5t9LIw0lqjY+rzeij2NRDf0=; b=DRVhSzZsPNOUVAwAQdU3ZfJkRqxYT5ooUQ0xzAZbyEd5BK+RK8v4wCu1oazuQetzeR xCsnZ3/Tn/Q1qs6Y6RjEN2j+Inu7kXf5lvv3ecHK3eluC3dclp8eTrdoWZUD1ZZ5HY3q mgLX0DoKZIp6IaFpDB2MuNMeVpUBIYPQseC7MZpACC/GQO7xt/SyPOAkBlcD5Y1dkfDS sMLRJes9UD7G88UbrMPPUp+h2GNHDHARzwGxHboygmkVk34LRMsZhM33VWYmiKT9rJgB Fe0R3FCb71AJcJZyu90zwFG+cCNzsRKj9/dMNgORreiL6Ske6HZOfYtqG/K0kFnvkzq/ bp/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cATzV+cgXA9fNf6+6osb5t9LIw0lqjY+rzeij2NRDf0=; b=NOZw/TlC54OiIRLxytzWMZBl+ovo+Ni90OO4+ENRc5Ymde3WE8zB2KWnTL9P0JMHhx +Eo48fj9rYPjAlAB60zCZEhMgrVpzezsrixpePOl9ACUti2EJJhiAITGto7IOLFIBi6d eg1FGfcojdFvoeFpbaKkMKyu3VgUi37ryz85bbvZCvnKLqJyLHZZ/AJ8C9i2RtOzgTpN AwpEr4sE8uXA5rjrltD1ZLvj2Q8a88RHjb6+rUILL99lbAWbd0uT/pY7K+F9JUzo7Kdu Nro+3eAe1rQdX11hy65nNb92p3jKum7so5vRPiHeUXyLyoBS4p2Hrc4FlbqS6qRsGDHB beMw== X-Gm-Message-State: AOAM530/2FR+hoNFjjsxoLUSHgmAowGrzkDVWXEKaUzLeCcP5inNDGut UN1rWxa+EDyXS4yq8Fl8xdomIq/c0erfF1+ZBIAmfw== X-Google-Smtp-Source: ABdhPJzCQnrZJVyyLjW6ViZm56nxlRoiIb9JOyCCs4FBdQe8rdlDPfVruz1UYu6Sr4ILLM1CDWpjyMkVVqOuUH+hdpo= X-Received: by 2002:a67:2dc6:: with SMTP id t189mr3914121vst.49.1630614396994; Thu, 02 Sep 2021 13:26:36 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-22-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-22-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:26:26 -0600 Message-ID: Subject: Re: [PATCH 21/24] target/rx: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Yoshinori Sato , Jiaxun Yang , qemu-arm , Palmer Dabbelt , Max Filippov , Michael Rolnik , Stafford Horne , Paolo Bonzini , "Edgar E. Iglesias" , Bin Meng , Chris Wulff , Mark Cave-Ayland , David Gibson , Kyle Evans , Peter Maydell , Aurelien Jarno , Eduardo Habkost , Marek Vasut , Artyom Tarasenko , Aleksandar Rikalo , Greg Kurz , qemu-riscv@nongnu.org, Laurent Vivier , qemu-ppc , Richard Henderson , Alistair Francis Content-Type: multipart/alternative; boundary="000000000000e61b4605cb08ff52" Received-SPF: none client-ip=2607:f8b0:4864:20::e31; envelope-from=wlosh@bsdimp.com; helo=mail-vs1-xe31.google.com X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Sep 2021 20:26:40 -0000 --000000000000e61b4605cb08ff52 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:19 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/rx/cpu.h | 2 ++ > target/rx/cpu.c | 2 +- > target/rx/helper.c | 4 ++++ > 3 files changed, 7 insertions(+), 1 deletion(-) > Reviewed-by: Warner Losh > diff --git a/target/rx/cpu.h b/target/rx/cpu.h > index 0b4b998c7be..faa3606f52f 100644 > --- a/target/rx/cpu.h > +++ b/target/rx/cpu.h > @@ -124,8 +124,10 @@ typedef RXCPU ArchCPU; > #define CPU_RESOLVING_TYPE TYPE_RX_CPU > > const char *rx_crname(uint8_t cr); > +#ifndef CONFIG_USER_ONLY > void rx_cpu_do_interrupt(CPUState *cpu); > bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); > +#endif /* !CONFIG_USER_ONLY */ > void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); > int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/rx/cpu.c b/target/rx/cpu.c > index 96cc96e514f..25a4aa2976d 100644 > --- a/target/rx/cpu.c > +++ b/target/rx/cpu.c > @@ -186,10 +186,10 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D = { > static const struct TCGCPUOps rx_tcg_ops =3D { > .initialize =3D rx_translate_init, > .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, > - .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, > .tlb_fill =3D rx_cpu_tlb_fill, > > #ifndef CONFIG_USER_ONLY > + .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, > .do_interrupt =3D rx_cpu_do_interrupt, > #endif /* !CONFIG_USER_ONLY */ > }; > diff --git a/target/rx/helper.c b/target/rx/helper.c > index db6b07e3890..f34945e7e2c 100644 > --- a/target/rx/helper.c > +++ b/target/rx/helper.c > @@ -40,6 +40,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, > int rte) > env->psw_c =3D FIELD_EX32(psw, PSW, C); > } > > +#ifndef CONFIG_USER_ONLY > + > #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) > void rx_cpu_do_interrupt(CPUState *cs) > { > @@ -142,6 +144,8 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int > interrupt_request) > return false; > } > > +#endif /* !CONFIG_USER_ONLY */ > + > hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > { > return addr; > -- > 2.31.1 > > --000000000000e61b4605cb08ff52 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:19 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/rx/cpu.h=C2=A0 =C2=A0 | 2 ++
=C2=A0target/rx/cpu.c=C2=A0 =C2=A0 | 2 +-
=C2=A0target/rx/helper.c | 4 ++++
=C2=A03 files changed, 7 insertions(+), 1 deletion(-)
=
Reviewed-by: Warner Losh <imp@bsdimp.com>

=C2=A0
=
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..faa3606f52f 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -124,8 +124,10 @@ typedef RXCPU ArchCPU;
=C2=A0#define CPU_RESOLVING_TYPE TYPE_RX_CPU

=C2=A0const char *rx_crname(uint8_t cr);
+#ifndef CONFIG_USER_ONLY
=C2=A0void rx_cpu_do_interrupt(CPUState *cpu);
=C2=A0bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
+#endif /* !CONFIG_USER_ONLY */
=C2=A0void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
=C2=A0int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)= ;
=C2=A0int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);<= br> diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 96cc96e514f..25a4aa2976d 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -186,10 +186,10 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D {<= br> =C2=A0static const struct TCGCPUOps rx_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.initialize =3D rx_translate_init,
=C2=A0 =C2=A0 =C2=A0.synchronize_from_tb =3D rx_cpu_synchronize_from_tb, -=C2=A0 =C2=A0 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D rx_cpu_tlb_fill,

=C2=A0#ifndef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D rx_cpu_do_interrupt,
=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
diff --git a/target/rx/helper.c b/target/rx/helper.c
index db6b07e3890..f34945e7e2c 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -40,6 +40,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int= rte)
=C2=A0 =C2=A0 =C2=A0env->psw_c =3D FIELD_EX32(psw, PSW, C);
=C2=A0}

+#ifndef CONFIG_USER_ONLY
+
=C2=A0#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
=C2=A0void rx_cpu_do_interrupt(CPUState *cs)
=C2=A0{
@@ -142,6 +144,8 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_= request)
=C2=A0 =C2=A0 =C2=A0return false;
=C2=A0}

+#endif /* !CONFIG_USER_ONLY */
+
=C2=A0hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0return addr;
--
2.31.1

--000000000000e61b4605cb08ff52--