From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 107EBC433F5 for ; Thu, 2 Sep 2021 20:27:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96BAF60F4B for ; Thu, 2 Sep 2021 20:27:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 96BAF60F4B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bsdimp.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:51584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLtIl-0006MT-LX for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 16:27:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLtGE-0003RD-OW for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:24:34 -0400 Received: from mail-vs1-xe29.google.com ([2607:f8b0:4864:20::e29]:35628) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLtGC-000584-PP for qemu-devel@nongnu.org; Thu, 02 Sep 2021 16:24:34 -0400 Received: by mail-vs1-xe29.google.com with SMTP id p14so2642505vsm.2 for ; Thu, 02 Sep 2021 13:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=O8Au4c7FKoaiiMWcGWVkJQlwfGHl1ua4n/AY/z3jDxg=; b=ygYzn8w7lHQ77vwd95mDffZz0nx3ggUnPStoVqrE68fm29Hz19TQ3h+t5Uglu+rZev RvohAJbyVuJO6hyqF5QwtAdpjyvO+zdT8otwVjp1nO69oxGK5Bz64X2usN2PRlESu+Ua 0kePoXWMcH0sPn3cL1QsyhL2efzEMdxe9ivKIO/4boUAWlCI2hlkakKsVNkQhlEx9Wk1 KLRsMG7bU430gSgF/QCDJ72sBpEzFFJfR3YSctbjiyCSaWASkZvXJINNidn+GsJoTXOV x2O1E43DJzVJo5Kmwl7LACoWwMyp5jgAWCSnNg5cSTijsZgVUUnZOxb6mLll/Cc2IwFS QrLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=O8Au4c7FKoaiiMWcGWVkJQlwfGHl1ua4n/AY/z3jDxg=; b=GP5yZ/GAGfuzS3b3gcDRNgPE+wroT/SoJ+JsVo5Z7H+g1K6YNyRqPyjvophk7spSWa A3JqZl0VJdEhIdQ31xdA3/rjttkQDAei6GSGGrHndT8n9C2SNiigj/Mb5B9A/Qk+KUUS iLxGIfhanw7vrj8vWMYsB91Gg8VgYF95LSrrFQjom38msZ2llLJb+SkjKXsxQtymMVpI +/03RJzNWYgM+bSiYqpdjzUFIMxfCydHqbLwpmemZht2q32/M4a6GtzUhCfAqwUsVfm/ TCRwmEu8hrcv906quwPTBUN+VJ6p4EwjWnJGZmIle4zCTtPh8oXrlWvEJYb+NBB5y1lW ZirQ== X-Gm-Message-State: AOAM531ZB1ufCI14I1otTIIZVcnHi+2dlgE3j7wMMICdp0oen3v/hI0Z KGcN6f8jKJnxkQ0UuGDqMCdrcPKeU/1WvVbUcr9N8w== X-Google-Smtp-Source: ABdhPJzP1rYW+Uga4iHnT/xVwapUcXCo3gEwp9XNO5GX6s9rIS/g56JFJ5GvesgZQp6sO/xDc8SY6QHqXxivEuQkGb4= X-Received: by 2002:a67:c789:: with SMTP id t9mr4350240vsk.60.1630614270890; Thu, 02 Sep 2021 13:24:30 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-17-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-17-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:24:20 -0600 Message-ID: Subject: Re: [PATCH 16/24] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: multipart/alternative; boundary="00000000000061e41f05cb08f8ff" Received-SPF: none client-ip=2607:f8b0:4864:20::e29; envelope-from=wlosh@bsdimp.com; helo=mail-vs1-xe29.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bin Meng , Mark Cave-Ayland , QEMU Developers , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , qemu-ppc , Artyom Tarasenko , Aleksandar Rikalo , Eduardo Habkost , Kyle Evans , Richard Henderson , Greg Kurz , qemu-arm , Michael Rolnik , Stafford Horne , David Gibson , qemu-riscv@nongnu.org, Chris Wulff , Laurent Vivier , Palmer Dabbelt , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000061e41f05cb08f8ff Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/openrisc/cpu.h | 5 +++-- > target/openrisc/cpu.c | 2 +- > target/openrisc/interrupt.c | 2 -- > target/openrisc/meson.build | 6 ++++-- > 4 files changed, 8 insertions(+), 7 deletions(-) > I'm not 100% sure about the build changes because my meson fu is weak, but they seem right given the rest. Reviewed-by: Warner Losh > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index 82cbaeb4f84..be6df81a810 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -312,8 +312,6 @@ struct OpenRISCCPU { > > > void cpu_openrisc_list(void); > -void openrisc_cpu_do_interrupt(CPUState *cpu); > -bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); > void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); > hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int > reg); > @@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info > *info); > #ifndef CONFIG_USER_ONLY > extern const VMStateDescription vmstate_openrisc_cpu; > > +void openrisc_cpu_do_interrupt(CPUState *cpu); > +bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); > + > /* hw/openrisc_pic.c */ > void cpu_openrisc_pic_init(OpenRISCCPU *cpu); > > diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c > index bd34e429ecb..27cb04152f9 100644 > --- a/target/openrisc/cpu.c > +++ b/target/openrisc/cpu.c > @@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_op= s > =3D { > > static const struct TCGCPUOps openrisc_tcg_ops =3D { > .initialize =3D openrisc_translate_init, > - .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, > .tlb_fill =3D openrisc_cpu_tlb_fill, > > #ifndef CONFIG_USER_ONLY > + .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, > .do_interrupt =3D openrisc_cpu_do_interrupt, > #endif /* !CONFIG_USER_ONLY */ > }; > diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c > index 3eab771dcda..19223e3f25b 100644 > --- a/target/openrisc/interrupt.c > +++ b/target/openrisc/interrupt.c > @@ -28,7 +28,6 @@ > > void openrisc_cpu_do_interrupt(CPUState *cs) > { > -#ifndef CONFIG_USER_ONLY > OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); > CPUOpenRISCState *env =3D &cpu->env; > int exception =3D cs->exception_index; > @@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) > } else { > cpu_abort(cs, "Unhandled exception 0x%x\n", exception); > } > -#endif > > cs->exception_index =3D -1; > } > diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build > index 9774a583065..e445dec4a00 100644 > --- a/target/openrisc/meson.build > +++ b/target/openrisc/meson.build > @@ -9,7 +9,6 @@ > 'exception_helper.c', > 'fpu_helper.c', > 'gdbstub.c', > - 'interrupt.c', > 'interrupt_helper.c', > 'mmu.c', > 'sys_helper.c', > @@ -17,7 +16,10 @@ > )) > > openrisc_softmmu_ss =3D ss.source_set() > -openrisc_softmmu_ss.add(files('machine.c')) > +openrisc_softmmu_ss.add(files( > + 'interrupt.c', > + 'machine.c', > +)) > > target_arch +=3D {'openrisc': openrisc_ss} > target_softmmu_arch +=3D {'openrisc': openrisc_softmmu_ss} > -- > 2.31.1 > > --00000000000061e41f05cb08f8ff Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:18 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/openrisc/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0| 5 +++--
=C2=A0target/openrisc/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0| 2 +-
=C2=A0target/openrisc/interrupt.c | 2 --
=C2=A0target/openrisc/meson.build | 6 ++++--
=C2=A04 files changed, 8 insertions(+), 7 deletions(-)

I'm not 100% sure about the build changes because my me= son fu is weak, but they seem right given the rest.=C2=A0

Reviewed-by: Warner Losh <imp@bsdimp.com>
=C2=A0
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..be6df81a810 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -312,8 +312,6 @@ struct OpenRISCCPU {


=C2=A0void cpu_openrisc_list(void);
-void openrisc_cpu_do_interrupt(CPUState *cpu);
-bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
=C2=A0void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
=C2=A0hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =C2=A0int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg);
@@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o);
=C2=A0#ifndef CONFIG_USER_ONLY
=C2=A0extern const VMStateDescription vmstate_openrisc_cpu;

+void openrisc_cpu_do_interrupt(CPUState *cpu);
+bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
=C2=A0/* hw/openrisc_pic.c */
=C2=A0void cpu_openrisc_pic_init(OpenRISCCPU *cpu);

diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index bd34e429ecb..27cb04152f9 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D {

=C2=A0static const struct TCGCPUOps openrisc_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.initialize =3D openrisc_translate_init,
-=C2=A0 =C2=A0 .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D openrisc_cpu_tlb_fill,

=C2=A0#ifndef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D openrisc_cpu_do_interrupt,
=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 3eab771dcda..19223e3f25b 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -28,7 +28,6 @@

=C2=A0void openrisc_cpu_do_interrupt(CPUState *cs)
=C2=A0{
-#ifndef CONFIG_USER_ONLY
=C2=A0 =C2=A0 =C2=A0OpenRISCCPU *cpu =3D OPENRISC_CPU(cs);
=C2=A0 =C2=A0 =C2=A0CPUOpenRISCState *env =3D &cpu->env;
=C2=A0 =C2=A0 =C2=A0int exception =3D cs->exception_index;
@@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_abort(cs, "Unhandled exception 0= x%x\n", exception);
=C2=A0 =C2=A0 =C2=A0}
-#endif

=C2=A0 =C2=A0 =C2=A0cs->exception_index =3D -1;
=C2=A0}
diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build
index 9774a583065..e445dec4a00 100644
--- a/target/openrisc/meson.build
+++ b/target/openrisc/meson.build
@@ -9,7 +9,6 @@
=C2=A0 =C2=A0'exception_helper.c',
=C2=A0 =C2=A0'fpu_helper.c',
=C2=A0 =C2=A0'gdbstub.c',
-=C2=A0 'interrupt.c',
=C2=A0 =C2=A0'interrupt_helper.c',
=C2=A0 =C2=A0'mmu.c',
=C2=A0 =C2=A0'sys_helper.c',
@@ -17,7 +16,10 @@
=C2=A0))

=C2=A0openrisc_softmmu_ss =3D ss.source_set()
-openrisc_softmmu_ss.add(files('machine.c'))
+openrisc_softmmu_ss.add(files(
+=C2=A0 'interrupt.c',
+=C2=A0 'machine.c',
+))

=C2=A0target_arch +=3D {'openrisc': openrisc_ss}
=C2=A0target_softmmu_arch +=3D {'openrisc': openrisc_softmmu_ss} --
2.31.1

--00000000000061e41f05cb08f8ff-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1mLtGG-0003UU-9q for mharc-qemu-riscv@gnu.org; Thu, 02 Sep 2021 16:24:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLtGE-0003Om-29 for qemu-riscv@nongnu.org; Thu, 02 Sep 2021 16:24:34 -0400 Received: from mail-vs1-xe36.google.com ([2607:f8b0:4864:20::e36]:35640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLtGC-000581-1a for qemu-riscv@nongnu.org; Thu, 02 Sep 2021 16:24:33 -0400 Received: by mail-vs1-xe36.google.com with SMTP id p14so2642504vsm.2 for ; Thu, 02 Sep 2021 13:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=O8Au4c7FKoaiiMWcGWVkJQlwfGHl1ua4n/AY/z3jDxg=; b=ygYzn8w7lHQ77vwd95mDffZz0nx3ggUnPStoVqrE68fm29Hz19TQ3h+t5Uglu+rZev RvohAJbyVuJO6hyqF5QwtAdpjyvO+zdT8otwVjp1nO69oxGK5Bz64X2usN2PRlESu+Ua 0kePoXWMcH0sPn3cL1QsyhL2efzEMdxe9ivKIO/4boUAWlCI2hlkakKsVNkQhlEx9Wk1 KLRsMG7bU430gSgF/QCDJ72sBpEzFFJfR3YSctbjiyCSaWASkZvXJINNidn+GsJoTXOV x2O1E43DJzVJo5Kmwl7LACoWwMyp5jgAWCSnNg5cSTijsZgVUUnZOxb6mLll/Cc2IwFS QrLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=O8Au4c7FKoaiiMWcGWVkJQlwfGHl1ua4n/AY/z3jDxg=; b=CA7zz36h8ngaq/mWp+raMsEwHR5fnbR7U5xd4YOjJ47eTSw3oTQ39i1wDkU8wv8Z9m B5qij9ESAfQrDaYVvT1AEsJifsFi3FfNEno5mCoBsyMAiPz2VfNEl2Qg4jTf9A7g+Iig UIQLf4dJvkMKFPuPEftbQWhZ7QQozqLpaPiwvW0X1RUiWbQHcbJsLGUcCMCn2Rhd12/X zgBVJ8g7AQrJiO0BxLyDoGjde4p+BANa3A8do5QYWlCRNaHOpAWsNKN2f1pj3w8Und0i hr/eNewmx9mJ2WL843HR3gvoLFDGVS6k0StFRY0jnyPEYjRSsa7BpKJpfJp0buPqisst K9cg== X-Gm-Message-State: AOAM530fY6QbL5dcXjLCqdtvV8gCTRYWA70zWERYsbVf7M5ByPltAhIw MdpTdhjQWLGDkhJTdgpYC5UUzs4djFeIe30SflQaDA== X-Google-Smtp-Source: ABdhPJzP1rYW+Uga4iHnT/xVwapUcXCo3gEwp9XNO5GX6s9rIS/g56JFJ5GvesgZQp6sO/xDc8SY6QHqXxivEuQkGb4= X-Received: by 2002:a67:c789:: with SMTP id t9mr4350240vsk.60.1630614270890; Thu, 02 Sep 2021 13:24:30 -0700 (PDT) MIME-Version: 1.0 References: <20210902151715.383678-1-f4bug@amsat.org> <20210902151715.383678-17-f4bug@amsat.org> In-Reply-To: <20210902151715.383678-17-f4bug@amsat.org> From: Warner Losh Date: Thu, 2 Sep 2021 14:24:20 -0600 Message-ID: Subject: Re: [PATCH 16/24] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: QEMU Developers , Yoshinori Sato , Jiaxun Yang , qemu-arm , Palmer Dabbelt , Max Filippov , Michael Rolnik , Stafford Horne , Paolo Bonzini , "Edgar E. Iglesias" , Bin Meng , Chris Wulff , Mark Cave-Ayland , David Gibson , Kyle Evans , Peter Maydell , Aurelien Jarno , Eduardo Habkost , Marek Vasut , Artyom Tarasenko , Aleksandar Rikalo , Greg Kurz , qemu-riscv@nongnu.org, Laurent Vivier , qemu-ppc , Richard Henderson , Alistair Francis Content-Type: multipart/alternative; boundary="00000000000061e41f05cb08f8ff" Received-SPF: none client-ip=2607:f8b0:4864:20::e36; envelope-from=wlosh@bsdimp.com; helo=mail-vs1-xe36.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Sep 2021 20:24:34 -0000 --00000000000061e41f05cb08f8ff Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Sep 2, 2021 at 9:18 AM Philippe Mathieu-Daud=C3=A9 wrote: > Restrict cpu_exec_interrupt() and its callees to sysemu. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > target/openrisc/cpu.h | 5 +++-- > target/openrisc/cpu.c | 2 +- > target/openrisc/interrupt.c | 2 -- > target/openrisc/meson.build | 6 ++++-- > 4 files changed, 8 insertions(+), 7 deletions(-) > I'm not 100% sure about the build changes because my meson fu is weak, but they seem right given the rest. Reviewed-by: Warner Losh > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index 82cbaeb4f84..be6df81a810 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -312,8 +312,6 @@ struct OpenRISCCPU { > > > void cpu_openrisc_list(void); > -void openrisc_cpu_do_interrupt(CPUState *cpu); > -bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); > void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); > hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); > int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int > reg); > @@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info > *info); > #ifndef CONFIG_USER_ONLY > extern const VMStateDescription vmstate_openrisc_cpu; > > +void openrisc_cpu_do_interrupt(CPUState *cpu); > +bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); > + > /* hw/openrisc_pic.c */ > void cpu_openrisc_pic_init(OpenRISCCPU *cpu); > > diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c > index bd34e429ecb..27cb04152f9 100644 > --- a/target/openrisc/cpu.c > +++ b/target/openrisc/cpu.c > @@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_op= s > =3D { > > static const struct TCGCPUOps openrisc_tcg_ops =3D { > .initialize =3D openrisc_translate_init, > - .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, > .tlb_fill =3D openrisc_cpu_tlb_fill, > > #ifndef CONFIG_USER_ONLY > + .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, > .do_interrupt =3D openrisc_cpu_do_interrupt, > #endif /* !CONFIG_USER_ONLY */ > }; > diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c > index 3eab771dcda..19223e3f25b 100644 > --- a/target/openrisc/interrupt.c > +++ b/target/openrisc/interrupt.c > @@ -28,7 +28,6 @@ > > void openrisc_cpu_do_interrupt(CPUState *cs) > { > -#ifndef CONFIG_USER_ONLY > OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); > CPUOpenRISCState *env =3D &cpu->env; > int exception =3D cs->exception_index; > @@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) > } else { > cpu_abort(cs, "Unhandled exception 0x%x\n", exception); > } > -#endif > > cs->exception_index =3D -1; > } > diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build > index 9774a583065..e445dec4a00 100644 > --- a/target/openrisc/meson.build > +++ b/target/openrisc/meson.build > @@ -9,7 +9,6 @@ > 'exception_helper.c', > 'fpu_helper.c', > 'gdbstub.c', > - 'interrupt.c', > 'interrupt_helper.c', > 'mmu.c', > 'sys_helper.c', > @@ -17,7 +16,10 @@ > )) > > openrisc_softmmu_ss =3D ss.source_set() > -openrisc_softmmu_ss.add(files('machine.c')) > +openrisc_softmmu_ss.add(files( > + 'interrupt.c', > + 'machine.c', > +)) > > target_arch +=3D {'openrisc': openrisc_ss} > target_softmmu_arch +=3D {'openrisc': openrisc_softmmu_ss} > -- > 2.31.1 > > --00000000000061e41f05cb08f8ff Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Sep 2, 2021 at 9:18 AM Philip= pe Mathieu-Daud=C3=A9 <f4bug@amsat.or= g> wrote:
Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
---
=C2=A0target/openrisc/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0| 5 +++--
=C2=A0target/openrisc/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0| 2 +-
=C2=A0target/openrisc/interrupt.c | 2 --
=C2=A0target/openrisc/meson.build | 6 ++++--
=C2=A04 files changed, 8 insertions(+), 7 deletions(-)

I'm not 100% sure about the build changes because my me= son fu is weak, but they seem right given the rest.=C2=A0

Reviewed-by: Warner Losh <imp@bsdimp.com>
=C2=A0
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..be6df81a810 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -312,8 +312,6 @@ struct OpenRISCCPU {


=C2=A0void cpu_openrisc_list(void);
-void openrisc_cpu_do_interrupt(CPUState *cpu);
-bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
=C2=A0void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
=C2=A0hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =C2=A0int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg);
@@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o);
=C2=A0#ifndef CONFIG_USER_ONLY
=C2=A0extern const VMStateDescription vmstate_openrisc_cpu;

+void openrisc_cpu_do_interrupt(CPUState *cpu);
+bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
=C2=A0/* hw/openrisc_pic.c */
=C2=A0void cpu_openrisc_pic_init(OpenRISCCPU *cpu);

diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index bd34e429ecb..27cb04152f9 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D {

=C2=A0static const struct TCGCPUOps openrisc_tcg_ops =3D {
=C2=A0 =C2=A0 =C2=A0.initialize =3D openrisc_translate_init,
-=C2=A0 =C2=A0 .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.tlb_fill =3D openrisc_cpu_tlb_fill,

=C2=A0#ifndef CONFIG_USER_ONLY
+=C2=A0 =C2=A0 .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt,
=C2=A0 =C2=A0 =C2=A0.do_interrupt =3D openrisc_cpu_do_interrupt,
=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 3eab771dcda..19223e3f25b 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -28,7 +28,6 @@

=C2=A0void openrisc_cpu_do_interrupt(CPUState *cs)
=C2=A0{
-#ifndef CONFIG_USER_ONLY
=C2=A0 =C2=A0 =C2=A0OpenRISCCPU *cpu =3D OPENRISC_CPU(cs);
=C2=A0 =C2=A0 =C2=A0CPUOpenRISCState *env =3D &cpu->env;
=C2=A0 =C2=A0 =C2=A0int exception =3D cs->exception_index;
@@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_abort(cs, "Unhandled exception 0= x%x\n", exception);
=C2=A0 =C2=A0 =C2=A0}
-#endif

=C2=A0 =C2=A0 =C2=A0cs->exception_index =3D -1;
=C2=A0}
diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build
index 9774a583065..e445dec4a00 100644
--- a/target/openrisc/meson.build
+++ b/target/openrisc/meson.build
@@ -9,7 +9,6 @@
=C2=A0 =C2=A0'exception_helper.c',
=C2=A0 =C2=A0'fpu_helper.c',
=C2=A0 =C2=A0'gdbstub.c',
-=C2=A0 'interrupt.c',
=C2=A0 =C2=A0'interrupt_helper.c',
=C2=A0 =C2=A0'mmu.c',
=C2=A0 =C2=A0'sys_helper.c',
@@ -17,7 +16,10 @@
=C2=A0))

=C2=A0openrisc_softmmu_ss =3D ss.source_set()
-openrisc_softmmu_ss.add(files('machine.c'))
+openrisc_softmmu_ss.add(files(
+=C2=A0 'interrupt.c',
+=C2=A0 'machine.c',
+))

=C2=A0target_arch +=3D {'openrisc': openrisc_ss}
=C2=A0target_softmmu_arch +=3D {'openrisc': openrisc_softmmu_ss} --
2.31.1

--00000000000061e41f05cb08f8ff--