From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0C9CC433E0 for ; Fri, 15 May 2020 14:52:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA833207BB for ; Fri, 15 May 2020 14:52:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UZ8+sJI+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726255AbgEOOwh (ORCPT ); Fri, 15 May 2020 10:52:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726144AbgEOOwg (ORCPT ); Fri, 15 May 2020 10:52:36 -0400 Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B3D8C061A0C for ; Fri, 15 May 2020 07:52:35 -0700 (PDT) Received: by mail-io1-xd44.google.com with SMTP id k18so3066680ion.0 for ; Fri, 15 May 2020 07:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vydHQTzj3c686TmTMHL1QqAtMRNRd4XB3MteF3kHgAs=; b=UZ8+sJI+p0f3is3kkpc69G6irKX6PH1tH/sgzavBs66A67D3Q6q/lwNTuPV3zb6U68 kqyrxtvEIkD7xcxvxSbLBvuowF52WJLwD3Ss7hSzlm66kdDyGCH1rpB63yzx+J5uHGcT ZEo3HnRA6MgTbSPk0O2J8ZLHIDgWLFLcxrCJLMU7oRNLQNXO9B9bgaIzsaINvzb92+2e HYHMjemU7Or55Oo6WkBlhT7O8JQd5nisDmoJ4k31ZH8J+2mulyDIfylPXwIxqZF1t8db +k+i08xW0fNlzPv6B0FXdlzkwrIobKrR06ywlxbxIX+C4SkvQTd0iuquFfGoKywD3Mmg 6wiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vydHQTzj3c686TmTMHL1QqAtMRNRd4XB3MteF3kHgAs=; b=idCNKpMO9pzCH7Dg+0LHCcxISafJqaSONfSlbGV0tUmYMv0rQy/ERfYJJ6vCVTOTTk ZTpuTssep7xDpPqXQCUXu/3lX5kNWlk7MsTupiYmfIhZ3eKxp4H4Soj/Wb7DLicv0hwT 4Fdwkz7FCawkA8+wT98MxzxbhNCFWWdlSm7TyhK0Z6MfQMSxwyggqPMH+Go1wH4AK6vR xF7cSezxHWiNUAtWIp5WJDqc4qYOpd8AMnRJuNgLFmwLt5x6CM6S/BmnEL6+az3qEn25 9WB2889Pa2lArl0pmi5J9UH5ZGjoOMYoUaaoBxxpx6F2wm/FSUkBgjUTKtxma8I/7Map /Z6A== X-Gm-Message-State: AOAM531xb+9XppwFkn4E8VqBOzlhsdxgYbrzUI76sm+G8HgTnhQ4l62m VRMZGTURQA8Eg0vqm+rCBxHGxKMnJRE+kWcbFpd4Nw== X-Google-Smtp-Source: ABdhPJyzKkiEkV8gyGv78TG2faQUaA8S/y2Gi7ZBEVgHXbh3X8djjspFmWdU7Sbf0WvFrTABd+a2aIxBe6daar4yk9U= X-Received: by 2002:a02:2708:: with SMTP id g8mr3682319jaa.52.1589554354623; Fri, 15 May 2020 07:52:34 -0700 (PDT) MIME-Version: 1.0 References: <20200514105915.27516-1-saiprakash.ranjan@codeaurora.org> <20200514180055.GA29384@xps15> <2c932d57288508cc72a6ee323cf5595e@codeaurora.org> In-Reply-To: <2c932d57288508cc72a6ee323cf5595e@codeaurora.org> From: Mathieu Poirier Date: Fri, 15 May 2020 08:52:23 -0600 Message-ID: Subject: Re: [PATCH] coresight: etm4x: Add support to disable trace unit power up To: Sai Prakash Ranjan Cc: Suzuki K Poulose , linux-arm-msm , Coresight ML , Linux Kernel Mailing List , Stephen Boyd , Tingwei Zhang , Leo Yan , linux-arm-kernel , Mike Leach Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan wrote: > > Hi Mathieu, > > On 2020-05-14 23:30, Mathieu Poirier wrote: > > Good morning Sai, > > > > On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote: > >> From: Tingwei Zhang > >> > >> On some Qualcomm Technologies Inc. SoCs like SC7180, there > >> exists a hardware errata where the APSS (Application Processor > >> SubSystem)/CPU watchdog counter is stopped when ETM register > >> TRCPDCR.PU=1. > > > > Fun stuff... > > > > Yes :) > > >> Since the ETMs share the same power domain as > >> that of respective CPU cores, they are powered on when the > >> CPU core is powered on. So we can disable powering up of the > >> trace unit after checking for this errata via new property > >> called "qcom,tupwr-disable". > >> > >> Signed-off-by: Tingwei Zhang > >> Co-developed-by: Sai Prakash Ranjan > >> Signed-off-by: Sai Prakash Ranjan > > > > Co-developed-by: Sai Prakash Ranjan > > Signed-off-by: Tingwei Zhang > > > > Tingwei is the author, so if I understand correctly, his signed-off-by > should appear first, am I wrong? It's a gray area and depends on who's code is more prevalent in the patch. If Tingwei wrote the most of the code then his name is in the "from:" section, yours as co-developer and he signs off on it (as I suggested). If you did most of the work then it is the opposite. Adding a Co-developed and a signed-off with the same name doesn't make sense. > > >> --- > >> .../devicetree/bindings/arm/coresight.txt | 6 ++++ > >> drivers/hwtracing/coresight/coresight-etm4x.c | 29 > >> ++++++++++++------- > > > > Please split in two patches. > > > > Sure, I will split the dt-binding into separate patch, checkpatch did > warn. And you still sent me the patch... I usually run checkpatch before all the submissions I review and flatly ignore patches that return errors. You got lucky... > > >> 2 files changed, 25 insertions(+), 10 deletions(-) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt > >> b/Documentation/devicetree/bindings/arm/coresight.txt > >> index 846f6daae71b..d2030128fe46 100644 > >> --- a/Documentation/devicetree/bindings/arm/coresight.txt > >> +++ b/Documentation/devicetree/bindings/arm/coresight.txt > >> @@ -108,6 +108,12 @@ its hardware characteristcs. > >> * arm,cp14: must be present if the system accesses ETM/PTM > >> management > >> registers via co-processor 14. > >> > >> + * qcom,tupwr-disable: boolean. Indicates that trace unit power up > >> can > >> + be disabled on Qualcomm Technologies Inc. systems where ETMs are > >> in > >> + the same power domain as their CPU cores. This property is > >> required > >> + to identify such systems with hardware errata where the CPU > >> watchdog > >> + counter is stopped when TRCPDCR.PU=1. > >> + > > > > I think something like "qcom,skip-power-up" would be clearer. > > > > Also, a better choice of words is that TRCPDCR.PU does not have to be > > set on > > Qualcomm... > > > > Yes "qcom,skip-power-up" is a lot better, thanks. Also will use > something as > you suggested for description. > > >> * Optional property for TMC: > >> > >> * arm,buffer-size: size of contiguous buffer space for TMC ETR > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c > >> b/drivers/hwtracing/coresight/coresight-etm4x.c > >> index fb0f5f4f3a91..6886b44f6947 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm4x.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > >> @@ -104,6 +104,11 @@ struct etm4_enable_arg { > >> int rc; > >> }; > >> > >> +static inline bool etm4_can_disable_tupwr(struct device *dev) > >> +{ > >> + return fwnode_property_present(dev_fwnode(dev), > >> "qcom,tupwr-disable"); > >> +} > >> + > > > > Please call fwnode_property_present() at initialisation time to set a > > new > > drvdata::skip_power_up variable. From there just switch on that in > > etm4_enable/disable_hw(). > > > > Will do, thanks. > > Thanks, > Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a > member > of Code Aurora Forum, hosted by The Linux Foundation > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33FF8C433E0 for ; Fri, 15 May 2020 14:52:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05E812076A for ; Fri, 15 May 2020 14:52:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="L7lqX3kx"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UZ8+sJI+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 05E812076A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4kSXOKDQhu866v1F/Q+vO3UArqZ6KT1F3kSiKDZL1bA=; b=L7lqX3kxfnuTdS v2jxhlfpgPhNIiwSVe6UCcexhL5vFT3fWpZNAgRlsj9Mt7DFXgCkFsPwsffXGEwhaGrAdN/2AWPYC 9yrwXesirOfUP2c1XqmUnWLR48PPZvkfDvXt5A7e8PyignUKu+aEy2zHO3YCl1skWyB0T7LWMD1Dr YMPt17aSX6egzLykdmT3w+ongOJRaXqJYo6y+QwbzHZiWHVKj0ZXAdRBh+197Qg2xPXVzZvU0HeZl sED6IfGF5KIN3tWYd4cMr2RZT9uVsVfLsjX8tSwVeSCwsYQG8qAbYlByTd6NcIfiWwZubwElTnE7r tl5AftucYaS3qulUwCXw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jZbhZ-0000Ll-9Q; Fri, 15 May 2020 14:52:41 +0000 Received: from mail-io1-xd42.google.com ([2607:f8b0:4864:20::d42]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jZbhU-0000Ki-AX for linux-arm-kernel@lists.infradead.org; Fri, 15 May 2020 14:52:39 +0000 Received: by mail-io1-xd42.google.com with SMTP id j8so2955766iog.13 for ; Fri, 15 May 2020 07:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vydHQTzj3c686TmTMHL1QqAtMRNRd4XB3MteF3kHgAs=; b=UZ8+sJI+p0f3is3kkpc69G6irKX6PH1tH/sgzavBs66A67D3Q6q/lwNTuPV3zb6U68 kqyrxtvEIkD7xcxvxSbLBvuowF52WJLwD3Ss7hSzlm66kdDyGCH1rpB63yzx+J5uHGcT ZEo3HnRA6MgTbSPk0O2J8ZLHIDgWLFLcxrCJLMU7oRNLQNXO9B9bgaIzsaINvzb92+2e HYHMjemU7Or55Oo6WkBlhT7O8JQd5nisDmoJ4k31ZH8J+2mulyDIfylPXwIxqZF1t8db +k+i08xW0fNlzPv6B0FXdlzkwrIobKrR06ywlxbxIX+C4SkvQTd0iuquFfGoKywD3Mmg 6wiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vydHQTzj3c686TmTMHL1QqAtMRNRd4XB3MteF3kHgAs=; b=khLadP1FjcxIAd/u7jBkUODxmtMDm2nsERDSQsdV51O1m0AZsuJ3J17JF7bpODg/LQ 7wNsCJJMCXQPzkLJ2Zhis4jgna1xG2DFxymDpmpYIvUSe3k5z9wr+C0Jgnmh+d3WXs09 eMm5UpSKiW0ZQjloIaV0fKM9HFJHFYrctr4S1tBNlLl3D+HymgUiHBJZEc96qjWkS9My qCDpihQ3ABMU0Qr0AzqbtKleElEqDXLBWOjfFqEx9RA6/cNUE4RLJz4H/zukWLKxeI34 fs6YQ6rzieFBzBzO3vEb8vwRsJxUcaMdxV5W8h3PQcnrRl8h8VZx6HK2STJVQVey45ov hVCQ== X-Gm-Message-State: AOAM531nkI2an/LEtLys45//3vUPHr4hifEJcTUlaLijY9Y5EEWUHtYD ngLtFay7n4iNH24V05Rj2/JF+CrTnVzrz7s2Cx9W5g== X-Google-Smtp-Source: ABdhPJyzKkiEkV8gyGv78TG2faQUaA8S/y2Gi7ZBEVgHXbh3X8djjspFmWdU7Sbf0WvFrTABd+a2aIxBe6daar4yk9U= X-Received: by 2002:a02:2708:: with SMTP id g8mr3682319jaa.52.1589554354623; Fri, 15 May 2020 07:52:34 -0700 (PDT) MIME-Version: 1.0 References: <20200514105915.27516-1-saiprakash.ranjan@codeaurora.org> <20200514180055.GA29384@xps15> <2c932d57288508cc72a6ee323cf5595e@codeaurora.org> In-Reply-To: <2c932d57288508cc72a6ee323cf5595e@codeaurora.org> From: Mathieu Poirier Date: Fri, 15 May 2020 08:52:23 -0600 Message-ID: Subject: Re: [PATCH] coresight: etm4x: Add support to disable trace unit power up To: Sai Prakash Ranjan X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200515_075236_366832_9BA6B300 X-CRM114-Status: GOOD ( 28.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , linux-arm-msm , Coresight ML , Linux Kernel Mailing List , Stephen Boyd , Tingwei Zhang , Leo Yan , linux-arm-kernel , Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan wrote: > > Hi Mathieu, > > On 2020-05-14 23:30, Mathieu Poirier wrote: > > Good morning Sai, > > > > On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote: > >> From: Tingwei Zhang > >> > >> On some Qualcomm Technologies Inc. SoCs like SC7180, there > >> exists a hardware errata where the APSS (Application Processor > >> SubSystem)/CPU watchdog counter is stopped when ETM register > >> TRCPDCR.PU=1. > > > > Fun stuff... > > > > Yes :) > > >> Since the ETMs share the same power domain as > >> that of respective CPU cores, they are powered on when the > >> CPU core is powered on. So we can disable powering up of the > >> trace unit after checking for this errata via new property > >> called "qcom,tupwr-disable". > >> > >> Signed-off-by: Tingwei Zhang > >> Co-developed-by: Sai Prakash Ranjan > >> Signed-off-by: Sai Prakash Ranjan > > > > Co-developed-by: Sai Prakash Ranjan > > Signed-off-by: Tingwei Zhang > > > > Tingwei is the author, so if I understand correctly, his signed-off-by > should appear first, am I wrong? It's a gray area and depends on who's code is more prevalent in the patch. If Tingwei wrote the most of the code then his name is in the "from:" section, yours as co-developer and he signs off on it (as I suggested). If you did most of the work then it is the opposite. Adding a Co-developed and a signed-off with the same name doesn't make sense. > > >> --- > >> .../devicetree/bindings/arm/coresight.txt | 6 ++++ > >> drivers/hwtracing/coresight/coresight-etm4x.c | 29 > >> ++++++++++++------- > > > > Please split in two patches. > > > > Sure, I will split the dt-binding into separate patch, checkpatch did > warn. And you still sent me the patch... I usually run checkpatch before all the submissions I review and flatly ignore patches that return errors. You got lucky... > > >> 2 files changed, 25 insertions(+), 10 deletions(-) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt > >> b/Documentation/devicetree/bindings/arm/coresight.txt > >> index 846f6daae71b..d2030128fe46 100644 > >> --- a/Documentation/devicetree/bindings/arm/coresight.txt > >> +++ b/Documentation/devicetree/bindings/arm/coresight.txt > >> @@ -108,6 +108,12 @@ its hardware characteristcs. > >> * arm,cp14: must be present if the system accesses ETM/PTM > >> management > >> registers via co-processor 14. > >> > >> + * qcom,tupwr-disable: boolean. Indicates that trace unit power up > >> can > >> + be disabled on Qualcomm Technologies Inc. systems where ETMs are > >> in > >> + the same power domain as their CPU cores. This property is > >> required > >> + to identify such systems with hardware errata where the CPU > >> watchdog > >> + counter is stopped when TRCPDCR.PU=1. > >> + > > > > I think something like "qcom,skip-power-up" would be clearer. > > > > Also, a better choice of words is that TRCPDCR.PU does not have to be > > set on > > Qualcomm... > > > > Yes "qcom,skip-power-up" is a lot better, thanks. Also will use > something as > you suggested for description. > > >> * Optional property for TMC: > >> > >> * arm,buffer-size: size of contiguous buffer space for TMC ETR > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c > >> b/drivers/hwtracing/coresight/coresight-etm4x.c > >> index fb0f5f4f3a91..6886b44f6947 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm4x.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > >> @@ -104,6 +104,11 @@ struct etm4_enable_arg { > >> int rc; > >> }; > >> > >> +static inline bool etm4_can_disable_tupwr(struct device *dev) > >> +{ > >> + return fwnode_property_present(dev_fwnode(dev), > >> "qcom,tupwr-disable"); > >> +} > >> + > > > > Please call fwnode_property_present() at initialisation time to set a > > new > > drvdata::skip_power_up variable. From there just switch on that in > > etm4_enable/disable_hw(). > > > > Will do, thanks. > > Thanks, > Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a > member > of Code Aurora Forum, hosted by The Linux Foundation > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel