From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753599AbcD0RWW (ORCPT ); Wed, 27 Apr 2016 13:22:22 -0400 Received: from mail-lf0-f52.google.com ([209.85.215.52]:35292 "EHLO mail-lf0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753492AbcD0RWV (ORCPT ); Wed, 27 Apr 2016 13:22:21 -0400 MIME-Version: 1.0 In-Reply-To: <5720A0AF.9090107@arm.com> References: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> <1461708634-6327-17-git-send-email-mathieu.poirier@linaro.org> <5720A0AF.9090107@arm.com> Date: Wed, 27 Apr 2016 11:22:19 -0600 Message-ID: Subject: Re: [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API From: Mathieu Poirier To: Suzuki K Poulose Cc: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27 April 2016 at 05:21, Suzuki K Poulose wrote: > On 26/04/16 23:10, Mathieu Poirier wrote: >> >> This patch implement the AUX area interfaces required to >> use the TMC (configured as an ETF) from the Perf sub-system. >> >> The heuristic is heavily borrowed from the ETB10 implementation. >> >> Signed-off-by: Mathieu Poirier > > >> + >> + /* >> + * Make sure the new size is aligned in accordance with >> the >> + * requirement explained above. >> + */ >> + to_read = handle->size & mask; >> + /* Move the RAM read pointer up */ >> + read_ptr = (write_ptr + drvdata->size) - to_read; >> + /* Make sure we are still within our limits */ >> + read_ptr &= ~(drvdata->size - 1); > > > Correct me if I am wrong, I think this will break for ETR configuration > (used from the following > patch 17/18). Since, for ETR, RRP/RWP will return the lower 32bit AXI > address (not the queue offset). > So the last step would really spoil the read_ptr. We might have to set the > read_ptr by adding the > appropriate offset from DBAL0. That's a very good catch. It also means we ETR support (17/18) has to be dropped from this set. I will do a respin of this patch only. Thanks, Mathieu > > Suzuki > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: mathieu.poirier@linaro.org (Mathieu Poirier) Date: Wed, 27 Apr 2016 11:22:19 -0600 Subject: [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API In-Reply-To: <5720A0AF.9090107@arm.com> References: <1461708634-6327-1-git-send-email-mathieu.poirier@linaro.org> <1461708634-6327-17-git-send-email-mathieu.poirier@linaro.org> <5720A0AF.9090107@arm.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 27 April 2016 at 05:21, Suzuki K Poulose wrote: > On 26/04/16 23:10, Mathieu Poirier wrote: >> >> This patch implement the AUX area interfaces required to >> use the TMC (configured as an ETF) from the Perf sub-system. >> >> The heuristic is heavily borrowed from the ETB10 implementation. >> >> Signed-off-by: Mathieu Poirier > > >> + >> + /* >> + * Make sure the new size is aligned in accordance with >> the >> + * requirement explained above. >> + */ >> + to_read = handle->size & mask; >> + /* Move the RAM read pointer up */ >> + read_ptr = (write_ptr + drvdata->size) - to_read; >> + /* Make sure we are still within our limits */ >> + read_ptr &= ~(drvdata->size - 1); > > > Correct me if I am wrong, I think this will break for ETR configuration > (used from the following > patch 17/18). Since, for ETR, RRP/RWP will return the lower 32bit AXI > address (not the queue offset). > So the last step would really spoil the read_ptr. We might have to set the > read_ptr by adding the > appropriate offset from DBAL0. That's a very good catch. It also means we ETR support (17/18) has to be dropped from this set. I will do a respin of this patch only. Thanks, Mathieu > > Suzuki > >