From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benson Leung Subject: Re: [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Date: Wed, 13 May 2015 17:29:28 -0700 Message-ID: References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> <1431451444-23155-20-git-send-email-rklein@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1431451444-23155-20-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rhyland Klein Cc: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: linux-tegra@vger.kernel.org On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein wrote: > This removes the conversion from pdiv to hw, which is already taken > care of by _get_table_rate before this code is run. This avoids > incorrectly converting pdiv to hw twice and getting the wrong hw value. > > Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while > setting all the other fields. > > Signed-off-by: Rhyland Klein Reviewed-by: Benson Leung -- Benson Leung Software Engineer, Chrom* OS bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965755AbbENA3x (ORCPT ); Wed, 13 May 2015 20:29:53 -0400 Received: from mail-ig0-f169.google.com ([209.85.213.169]:36512 "EHLO mail-ig0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753182AbbENA32 (ORCPT ); Wed, 13 May 2015 20:29:28 -0400 MIME-Version: 1.0 In-Reply-To: <1431451444-23155-20-git-send-email-rklein@nvidia.com> References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> <1431451444-23155-20-git-send-email-rklein@nvidia.com> Date: Wed, 13 May 2015 17:29:28 -0700 X-Google-Sender-Auth: CctzMMhCHsYgd23ei6YXR6856V4 Message-ID: Subject: Re: [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate From: Benson Leung To: Rhyland Klein Cc: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein wrote: > This removes the conversion from pdiv to hw, which is already taken > care of by _get_table_rate before this code is run. This avoids > incorrectly converting pdiv to hw twice and getting the wrong hw value. > > Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while > setting all the other fields. > > Signed-off-by: Rhyland Klein Reviewed-by: Benson Leung -- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org