From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benson Leung Subject: Re: [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs Date: Thu, 14 May 2015 13:02:56 -0700 Message-ID: References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> <1431451444-23155-23-git-send-email-rklein@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <1431451444-23155-23-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rhyland Klein Cc: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Andrew Bresticker List-Id: linux-tegra@vger.kernel.org On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein wrote: > From: Andrew Bresticker > > Without this change clk_get_rate would return the final output > rather than the VCO output as it would factor in the pdiv when > it shouldn't. This will cause problems for all dividers in the > subtree of the VCO PLL. > > Signed-off-by: Andrew Bresticker > Signed-off-by: Rhyland Klein Reviewed-by: Benson Leung -- Benson Leung Software Engineer, Chrom* OS bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965178AbbENUDA (ORCPT ); Thu, 14 May 2015 16:03:00 -0400 Received: from mail-ie0-f180.google.com ([209.85.223.180]:34391 "EHLO mail-ie0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965045AbbENUC5 (ORCPT ); Thu, 14 May 2015 16:02:57 -0400 MIME-Version: 1.0 In-Reply-To: <1431451444-23155-23-git-send-email-rklein@nvidia.com> References: <1431451444-23155-1-git-send-email-rklein@nvidia.com> <1431451444-23155-23-git-send-email-rklein@nvidia.com> Date: Thu, 14 May 2015 13:02:56 -0700 X-Google-Sender-Auth: X6-bSixlz_WJ9BNXym-jDboScrA Message-ID: Subject: Re: [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs From: Benson Leung To: Rhyland Klein Cc: Peter De Schrijver , Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , Bill Huang , Paul Walmsley , Jim Lin , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" , Andrew Bresticker Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein wrote: > From: Andrew Bresticker > > Without this change clk_get_rate would return the final output > rather than the VCO output as it would factor in the pdiv when > it shouldn't. This will cause problems for all dividers in the > subtree of the VCO PLL. > > Signed-off-by: Andrew Bresticker > Signed-off-by: Rhyland Klein Reviewed-by: Benson Leung -- Benson Leung Software Engineer, Chrom* OS bleung@chromium.org