From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=/s9R=UY=vger.kernel.org=linux-kernel-owner@kernel.org>
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
	aws-us-west-2-korg-lkml-1.web.codeaurora.org
X-Spam-Level: 
X-Spam-Status: No, score=-4.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,
	DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,
	MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,
	UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=ham autolearn_force=no
	version=3.4.0
Received: from mail.kernel.org (mail.kernel.org [198.145.29.99])
	by smtp.lore.kernel.org (Postfix) with ESMTP id 0ADE9C4646C
	for <linux-kernel@archiver.kernel.org>; Tue, 25 Jun 2019 00:42:32 +0000 (UTC)
Received: from vger.kernel.org (vger.kernel.org [209.132.180.67])
	by mail.kernel.org (Postfix) with ESMTP id C527620665
	for <linux-kernel@archiver.kernel.org>; Tue, 25 Jun 2019 00:42:31 +0000 (UTC)
Authentication-Results: mail.kernel.org;
	dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="a78p5hkW"
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1729384AbfFYAma (ORCPT
        <rfc822;linux-kernel@archiver.kernel.org>);
        Mon, 24 Jun 2019 20:42:30 -0400
Received: from mail-qt1-f195.google.com ([209.85.160.195]:42054 "EHLO
        mail-qt1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1729029AbfFYAma (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Mon, 24 Jun 2019 20:42:30 -0400
Received: by mail-qt1-f195.google.com with SMTP id s15so16539398qtk.9
        for <linux-kernel@vger.kernel.org>; Mon, 24 Jun 2019 17:42:28 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=chromium.org; s=google;
        h=mime-version:references:in-reply-to:from:date:message-id:subject:to
         :cc;
        bh=D0CatzhMtPEqvzuGSZZ/Q3MqqvQzjh5y8rhA8hbW6wI=;
        b=a78p5hkWEU9pITE2WlOzVrvy1+Bd3DoHqUYTxcohn3/jicZ4BT1bVNTF0ZkH4EanZM
         /MGTT4aGn774EQzPilUErLwm6/larBYmP9L67V7pGknpqwcoDRvSoK+UimzH/9Cwkz5n
         JDQoSlMatN3leySyGnMtW2vgdGcu/a25fH8OA=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=1e100.net; s=20161025;
        h=x-gm-message-state:mime-version:references:in-reply-to:from:date
         :message-id:subject:to:cc;
        bh=D0CatzhMtPEqvzuGSZZ/Q3MqqvQzjh5y8rhA8hbW6wI=;
        b=T5S3AeN2M8U/L/GZ/4QxztjjHLFkXAOrEtIjLoYOkNa50s+P3Zkwm4lmMwR3bK/BRg
         o+CKp6MBHfPwI1vBQREPp2huN4Q1AcHuDG1YuYatiu+UE+m8B/d09YT26eqRuh0Oi47P
         UK/RRex/WtmIIMC4BWpykS8t7G2bGU1kTZADg2mToTutTXm/UgBhqpMmI0ocwIyXVMaP
         IVazA/S31ItnEIO9FbCWlkrwP3eA2zN+OnCxtavTvde5vm5M51z1g1xxzlkixshCH9z6
         DSCBmHK4S/uX1/orQM2Vxejob9P2OWrsk+hwSQ1fEIwQwv2VGnXw4nNR8uwFGCorI1n5
         wFMQ==
X-Gm-Message-State: APjAAAXyNxRnXC3SI2fN431PjCETyhrA/ySAntEafYNzj/sd/aeYzQ2s
        2/9xIq60o8tM9i5l7p/e+yEtSSW7TH6/FbxluCrxyA==
X-Google-Smtp-Source: APXvYqz89tH5leyNwSwZvrzbPI8hzk5ZFa+L9cXsOqWm3c0MO/uRmaRHdIt4onolh51eRNIVIZpsb78QxJME3gZZLNY=
X-Received: by 2002:a0c:b04d:: with SMTP id l13mr61365864qvc.104.1561423348081;
 Mon, 24 Jun 2019 17:42:28 -0700 (PDT)
MIME-Version: 1.0
References: <20190624060343.62451-1-jitao.shi@mediatek.com>
 <20190624060343.62451-3-jitao.shi@mediatek.com> <CANMq1KABzuKu1nyP4Mq-6eHPA3tFZ+AViAaouzrgHu9RL4i-6A@mail.gmail.com>
In-Reply-To: <CANMq1KABzuKu1nyP4Mq-6eHPA3tFZ+AViAaouzrgHu9RL4i-6A@mail.gmail.com>
From:   Nicolas Boichat <drinkcat@chromium.org>
Date:   Tue, 25 Jun 2019 08:42:16 +0800
Message-ID: <CANMq1KBS0DhVcM=EMqNQfMuh91WJ-Vk5EZvVKkLQQq2VECjraA@mail.gmail.com>
Subject: Re: [v2 2/2] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video
 mode panel
To:     Jitao Shi <jitao.shi@mediatek.com>
Cc:     Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        linux-pwm@vger.kernel.org, David Airlie <airlied@linux.ie>,
        Matthias Brugger <matthias.bgg@gmail.com>, stonea168@163.com,
        dri-devel@lists.freedesktop.org,
        Andy Yan <andy.yan@rock-chips.com>,
        Ajay Kumar <ajaykumar.rs@samsung.com>,
        Vincent Palatin <vpalatin@chromium.org>,
        cawa cheng <cawa.cheng@mediatek.com>,
        Russell King <rmk+kernel@arm.linux.org.uk>,
        Thierry Reding <treding@nvidia.com>,
        devicetree@vger.kernel.org,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        Yingjoe Chen <yingjoe.chen@mediatek.com>,
        Eddie Huang <eddie.huang@mediatek.com>,
        linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
        Rahul Sharma <rahul.sharma@samsung.com>,
        srv_heupstream <srv_heupstream@mediatek.com>,
        lkml <linux-kernel@vger.kernel.org>,
        Sascha Hauer <kernel@pengutronix.de>,
        Sean Paul <seanpaul@chromium.org>
Content-Type: text/plain; charset="UTF-8"
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, Jun 24, 2019 at 4:25 PM Nicolas Boichat <drinkcat@chromium.org> wrote:
>
> On Mon, Jun 24, 2019 at 2:04 PM Jitao Shi <jitao.shi@mediatek.com> wrote:
> >
> > Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.
> >
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > ---
> >  drivers/gpu/drm/panel/Kconfig                 |  10 +
> >  drivers/gpu/drm/panel/Makefile                |   1 +
> >  .../gpu/drm/panel/panel-boe-tv101wum-nl6.c    | 715 ++++++++++++++++++
> >  3 files changed, 726 insertions(+)
> >  create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> >
> > diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> > index e36dbb4df867..2b055ce0700b 100644
> > --- a/drivers/gpu/drm/panel/Kconfig
> > +++ b/drivers/gpu/drm/panel/Kconfig
> > @@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
> >           reference designs. The panel is detected using special registers
> >           in the Versatile family syscon registers.
> >
> > +config DRM_PANEL_BOE_TV101WUM_NL6
> > +       tristate "BOE TV101WUM 1200x1920 panel"
> > +       depends on OF
> > +       depends on DRM_MIPI_DSI
> > +       depends on BACKLIGHT_CLASS_DEVICE
> > +       help
> > +         Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
> > +         DSI Video Mode panel
> > +
> >  config DRM_PANEL_LVDS
> >         tristate "Generic LVDS panel driver"
> >         depends on OF
> > @@ -272,4 +281,5 @@ config DRM_PANEL_TRULY_NT35597_WQXGA
> >         help
> >           Say Y here if you want to enable support for Truly NT35597 WQXGA Dual DSI
> >           Video Mode panel
> > +
>
> Drop this change.
>
> >  endmenu
> > diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> > index 78e3dc376bdd..8d009223c44e 100644
> > --- a/drivers/gpu/drm/panel/Makefile
> > +++ b/drivers/gpu/drm/panel/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
> > +obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
> >  obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
> >  obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
> >  obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
> > diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > new file mode 100644
> > index 000000000000..6e06c8506623
> > --- /dev/null
> > +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > @@ -0,0 +1,715 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Jitao Shi <jitao.shi@mediatek.com>
> > + */
> > +
> > +#include <linux/backlight.h>
> > +#include <linux/delay.h>
> > +#include <linux/gpio/consumer.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/regulator/consumer.h>
> > +
> > +#include <drm/drm_crtc.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +#include <drm/drm_panel.h>
> > +
> > +#include <video/mipi_display.h>
> > +
> > +struct panel_desc {
> > +       const struct drm_display_mode *modes;
> > +       unsigned int bpc;
> > +
> > +       /**
> > +        * @width: width (in millimeters) of the panel's active display area
> > +        * @height: height (in millimeters) of the panel's active display area
> > +        */
> > +       struct {
> > +               unsigned int width;
> > +               unsigned int height;
> > +       } size;
> > +
> > +       unsigned long mode_flags;
> > +       enum mipi_dsi_pixel_format format;
> > +       const struct panel_init_cmd *init_cmds;
> > +       unsigned int lanes;
> > +};
> > +
> > +struct boe_panel {
> > +       struct drm_panel base;
> > +       struct mipi_dsi_device *dsi;
> > +
> > +       const struct panel_desc *desc;
> > +
> > +       struct backlight_device *backlight;
> > +       struct regulator *pp1800;
> > +       struct regulator *avee;
> > +       struct regulator *avdd;
> > +       struct gpio_desc *enable_gpio;
> > +
> > +       bool prepared;
> > +       bool enabled;
> > +
> > +       const struct drm_display_mode *mode;
> > +};
> > +
> > +enum dsi_cmd_type {
> > +       INIT_DCS_CMD,
> > +       DELAY_CMD,
> > +};
> > +
> > +struct panel_init_cmd {
> > +       enum dsi_cmd_type type;
> > +       size_t len;
> > +       const char *data;
> > +};
> > +
> > +#define _INIT_DCS_CMD(...) { \
> > +       .type = INIT_DCS_CMD, \
> > +       .len = sizeof((char[]){__VA_ARGS__}), \
> > +       .data = (char[]){__VA_ARGS__} }
> > +
> > +#define _INIT_DELAY_CMD(...) { \
> > +       .type = DELAY_CMD,\
> > +       .len = sizeof((char[]){__VA_ARGS__}), \
> > +       .data = (char[]){__VA_ARGS__} }
> > +
> > +static const struct panel_init_cmd boe_init_cmd[] = {
> > +       _INIT_DELAY_CMD(24),
> > +       _INIT_DCS_CMD(0xB0, 0x05),
> > +       _INIT_DCS_CMD(0xB1, 0xE5),
> > +       _INIT_DCS_CMD(0xB3, 0x52),
> > +       _INIT_DCS_CMD(0xB0, 0x00),
> > +       _INIT_DCS_CMD(0xB3, 0x88),
> > +       _INIT_DCS_CMD(0xB0, 0x04),
> > +       _INIT_DCS_CMD(0xB8, 0x00),
> > +       _INIT_DCS_CMD(0xB0, 0x00),
> > +       _INIT_DCS_CMD(0xB6, 0x03),
> > +       _INIT_DCS_CMD(0xBA, 0x8B),
> > +       _INIT_DCS_CMD(0xBF, 0x1A),
> > +       _INIT_DCS_CMD(0xC0, 0x0F),
> > +       _INIT_DCS_CMD(0xC2, 0x0C),
> > +       _INIT_DCS_CMD(0xC3, 0x02),
> > +       _INIT_DCS_CMD(0xC4, 0x0C),
> > +       _INIT_DCS_CMD(0xC5, 0x02),
> > +       _INIT_DCS_CMD(0xB0, 0x01),
> > +       _INIT_DCS_CMD(0xE0, 0x26),
> > +       _INIT_DCS_CMD(0xE1, 0x26),
> > +       _INIT_DCS_CMD(0xDC, 0x00),
> > +       _INIT_DCS_CMD(0xDD, 0x00),
> > +       _INIT_DCS_CMD(0xCC, 0x26),
> > +       _INIT_DCS_CMD(0xCD, 0x26),
> > +       _INIT_DCS_CMD(0xC8, 0x00),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xD2, 0x03),
> > +       _INIT_DCS_CMD(0xD3, 0x03),
> > +       _INIT_DCS_CMD(0xE6, 0x04),
> > +       _INIT_DCS_CMD(0xE7, 0x04),
> > +       _INIT_DCS_CMD(0xC4, 0x09),
> > +       _INIT_DCS_CMD(0xC5, 0x09),
> > +       _INIT_DCS_CMD(0xD8, 0x0A),
> > +       _INIT_DCS_CMD(0xD9, 0x0A),
> > +       _INIT_DCS_CMD(0xC2, 0x0B),
> > +       _INIT_DCS_CMD(0xC3, 0x0B),
> > +       _INIT_DCS_CMD(0xD6, 0x0C),
> > +       _INIT_DCS_CMD(0xD7, 0x0C),
> > +       _INIT_DCS_CMD(0xC0, 0x05),
> > +       _INIT_DCS_CMD(0xC1, 0x05),
> > +       _INIT_DCS_CMD(0xD4, 0x06),
> > +       _INIT_DCS_CMD(0xD5, 0x06),
> > +       _INIT_DCS_CMD(0xCA, 0x07),
> > +       _INIT_DCS_CMD(0xCB, 0x07),
> > +       _INIT_DCS_CMD(0xDE, 0x08),
> > +       _INIT_DCS_CMD(0xDF, 0x08),
> > +       _INIT_DCS_CMD(0xB0, 0x02),
> > +       _INIT_DCS_CMD(0xC0, 0x00),
> > +       _INIT_DCS_CMD(0xC1, 0x0D),
> > +       _INIT_DCS_CMD(0xC2, 0x17),
> > +       _INIT_DCS_CMD(0xC3, 0x26),
> > +       _INIT_DCS_CMD(0xC4, 0x31),
> > +       _INIT_DCS_CMD(0xC5, 0x1C),
> > +       _INIT_DCS_CMD(0xC6, 0x2C),
> > +       _INIT_DCS_CMD(0xC7, 0x33),
> > +       _INIT_DCS_CMD(0xC8, 0x31),
> > +       _INIT_DCS_CMD(0xC9, 0x37),
> > +       _INIT_DCS_CMD(0xCA, 0x37),
> > +       _INIT_DCS_CMD(0xCB, 0x37),
> > +       _INIT_DCS_CMD(0xCC, 0x39),
> > +       _INIT_DCS_CMD(0xCD, 0x2E),
> > +       _INIT_DCS_CMD(0xCE, 0x2F),
> > +       _INIT_DCS_CMD(0xCF, 0x2F),
> > +       _INIT_DCS_CMD(0xD0, 0x07),
> > +       _INIT_DCS_CMD(0xD2, 0x00),
> > +       _INIT_DCS_CMD(0xD3, 0x0D),
> > +       _INIT_DCS_CMD(0xD4, 0x17),
> > +       _INIT_DCS_CMD(0xD5, 0x26),
> > +       _INIT_DCS_CMD(0xD6, 0x31),
> > +       _INIT_DCS_CMD(0xD7, 0x3F),
> > +       _INIT_DCS_CMD(0xD8, 0x3F),
> > +       _INIT_DCS_CMD(0xD9, 0x3F),
> > +       _INIT_DCS_CMD(0xDA, 0x3F),
> > +       _INIT_DCS_CMD(0xDB, 0x37),
> > +       _INIT_DCS_CMD(0xDC, 0x37),
> > +       _INIT_DCS_CMD(0xDD, 0x37),
> > +       _INIT_DCS_CMD(0xDE, 0x39),
> > +       _INIT_DCS_CMD(0xDF, 0x2E),
> > +       _INIT_DCS_CMD(0xE0, 0x2F),
> > +       _INIT_DCS_CMD(0xE1, 0x2F),
> > +       _INIT_DCS_CMD(0xE2, 0x07),
> > +       _INIT_DCS_CMD(0xB0, 0x03),
> > +       _INIT_DCS_CMD(0xC8, 0x0B),
> > +       _INIT_DCS_CMD(0xC9, 0x07),
> > +       _INIT_DCS_CMD(0xC3, 0x00),
> > +       _INIT_DCS_CMD(0xE7, 0x00),
> > +       _INIT_DCS_CMD(0xC5, 0x2A),
> > +       _INIT_DCS_CMD(0xDE, 0x2A),
> > +       _INIT_DCS_CMD(0xCA, 0x43),
> > +       _INIT_DCS_CMD(0xC9, 0x07),
> > +       _INIT_DCS_CMD(0xE4, 0xC0),
> > +       _INIT_DCS_CMD(0xE5, 0x0D),
> > +       _INIT_DCS_CMD(0xCB, 0x00),
> > +       _INIT_DCS_CMD(0xB0, 0x06),
> > +       _INIT_DCS_CMD(0xB8, 0xA5),
> > +       _INIT_DCS_CMD(0xC0, 0xA5),
> > +       _INIT_DCS_CMD(0xC7, 0x0F),
> > +       _INIT_DCS_CMD(0xD5, 0x32),
> > +       _INIT_DCS_CMD(0xB8, 0x00),
> > +       _INIT_DCS_CMD(0xC0, 0x00),
> > +       _INIT_DCS_CMD(0xBC, 0x00),
> > +       _INIT_DCS_CMD(0xB0, 0x07),
> > +       _INIT_DCS_CMD(0xB1, 0x00),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x0F),
> > +       _INIT_DCS_CMD(0xB4, 0x25),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4E),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x97),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x22),
> > +       _INIT_DCS_CMD(0xBB, 0xA4),
> > +       _INIT_DCS_CMD(0xBC, 0x2B),
> > +       _INIT_DCS_CMD(0xBD, 0x2F),
> > +       _INIT_DCS_CMD(0xBE, 0xA9),
> > +       _INIT_DCS_CMD(0xBF, 0x25),
> > +       _INIT_DCS_CMD(0xC0, 0x61),
> > +       _INIT_DCS_CMD(0xC1, 0x97),
> > +       _INIT_DCS_CMD(0xC2, 0xB2),
> > +       _INIT_DCS_CMD(0xC3, 0xCD),
> > +       _INIT_DCS_CMD(0xC4, 0xD9),
> > +       _INIT_DCS_CMD(0xC5, 0xE7),
> > +       _INIT_DCS_CMD(0xC6, 0xF4),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x08),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x05),
> > +       _INIT_DCS_CMD(0xB3, 0x11),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x98),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x23),
> > +       _INIT_DCS_CMD(0xBB, 0xA6),
> > +       _INIT_DCS_CMD(0xBC, 0x2C),
> > +       _INIT_DCS_CMD(0xBD, 0x30),
> > +       _INIT_DCS_CMD(0xBE, 0xAA),
> > +       _INIT_DCS_CMD(0xBF, 0x26),
> > +       _INIT_DCS_CMD(0xC0, 0x62),
> > +       _INIT_DCS_CMD(0xC1, 0x9B),
> > +       _INIT_DCS_CMD(0xC2, 0xB5),
> > +       _INIT_DCS_CMD(0xC3, 0xCF),
> > +       _INIT_DCS_CMD(0xC4, 0xDB),
> > +       _INIT_DCS_CMD(0xC5, 0xE8),
> > +       _INIT_DCS_CMD(0xC6, 0xF5),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x09),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x16),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x3B),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x73),
> > +       _INIT_DCS_CMD(0xB8, 0x99),
> > +       _INIT_DCS_CMD(0xB9, 0xE0),
> > +       _INIT_DCS_CMD(0xBA, 0x26),
> > +       _INIT_DCS_CMD(0xBB, 0xAD),
> > +       _INIT_DCS_CMD(0xBC, 0x36),
> > +       _INIT_DCS_CMD(0xBD, 0x3A),
> > +       _INIT_DCS_CMD(0xBE, 0xAE),
> > +       _INIT_DCS_CMD(0xBF, 0x2A),
> > +       _INIT_DCS_CMD(0xC0, 0x66),
> > +       _INIT_DCS_CMD(0xC1, 0x9E),
> > +       _INIT_DCS_CMD(0xC2, 0xB8),
> > +       _INIT_DCS_CMD(0xC3, 0xD1),
> > +       _INIT_DCS_CMD(0xC4, 0xDD),
> > +       _INIT_DCS_CMD(0xC5, 0xE9),
> > +       _INIT_DCS_CMD(0xC6, 0xF6),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x0A),
> > +       _INIT_DCS_CMD(0xB1, 0x00),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x0F),
> > +       _INIT_DCS_CMD(0xB4, 0x25),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4E),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x97),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x22),
> > +       _INIT_DCS_CMD(0xBB, 0xA4),
> > +       _INIT_DCS_CMD(0xBC, 0x2B),
> > +       _INIT_DCS_CMD(0xBD, 0x2F),
> > +       _INIT_DCS_CMD(0xBE, 0xA9),
> > +       _INIT_DCS_CMD(0xBF, 0x25),
> > +       _INIT_DCS_CMD(0xC0, 0x61),
> > +       _INIT_DCS_CMD(0xC1, 0x97),
> > +       _INIT_DCS_CMD(0xC2, 0xB2),
> > +       _INIT_DCS_CMD(0xC3, 0xCD),
> > +       _INIT_DCS_CMD(0xC4, 0xD9),
> > +       _INIT_DCS_CMD(0xC5, 0xE7),
> > +       _INIT_DCS_CMD(0xC6, 0xF4),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x0B),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x05),
> > +       _INIT_DCS_CMD(0xB3, 0x11),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x98),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x23),
> > +       _INIT_DCS_CMD(0xBB, 0xA6),
> > +       _INIT_DCS_CMD(0xBC, 0x2C),
> > +       _INIT_DCS_CMD(0xBD, 0x30),
> > +       _INIT_DCS_CMD(0xBE, 0xAA),
> > +       _INIT_DCS_CMD(0xBF, 0x26),
> > +       _INIT_DCS_CMD(0xC0, 0x62),
> > +       _INIT_DCS_CMD(0xC1, 0x9B),
> > +       _INIT_DCS_CMD(0xC2, 0xB5),
> > +       _INIT_DCS_CMD(0xC3, 0xCF),
> > +       _INIT_DCS_CMD(0xC4, 0xDB),
> > +       _INIT_DCS_CMD(0xC5, 0xE8),
> > +       _INIT_DCS_CMD(0xC6, 0xF5),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x0C),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x16),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x3B),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x73),
> > +       _INIT_DCS_CMD(0xB8, 0x99),
> > +       _INIT_DCS_CMD(0xB9, 0xE0),
> > +       _INIT_DCS_CMD(0xBA, 0x26),
> > +       _INIT_DCS_CMD(0xBB, 0xAD),
> > +       _INIT_DCS_CMD(0xBC, 0x36),
> > +       _INIT_DCS_CMD(0xBD, 0x3A),
> > +       _INIT_DCS_CMD(0xBE, 0xAE),
> > +       _INIT_DCS_CMD(0xBF, 0x2A),
> > +       _INIT_DCS_CMD(0xC0, 0x66),
> > +       _INIT_DCS_CMD(0xC1, 0x9E),
> > +       _INIT_DCS_CMD(0xC2, 0xB8),
> > +       _INIT_DCS_CMD(0xC3, 0xD1),
> > +       _INIT_DCS_CMD(0xC4, 0xDD),
> > +       _INIT_DCS_CMD(0xC5, 0xE9),
> > +       _INIT_DCS_CMD(0xC6, 0xF6),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x00),
> > +       _INIT_DCS_CMD(0xB3, 0x08),
> > +       _INIT_DCS_CMD(0xB0, 0x04),
> > +       _INIT_DCS_CMD(0xB8, 0x68),
> > +       _INIT_DELAY_CMD(150),
> > +       {},
> > +};
> > +
> > +static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
> > +{
> > +       return container_of(panel, struct boe_panel, base);
> > +}
> > +
> > +static int boe_panel_init(struct boe_panel *boe)
> > +{
> > +       struct mipi_dsi_device *dsi = boe->dsi;
> > +       struct drm_panel *panel = &boe->base;
> > +       int err, i;
> > +
> > +       if (boe->desc->init_cmds) {
> > +               const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
> > +
> > +               for (i = 0; init_cmds[i].len != 0; i++) {
> > +                       const struct panel_init_cmd *cmd = &init_cmds[i];
> > +
> > +                       switch (cmd->type) {
> > +                       case DELAY_CMD:
> > +                               msleep(cmd->data[0]);
> > +                               err = 0;
> > +                               break;
> > +
> > +                       case INIT_DCS_CMD:
> > +                               err = mipi_dsi_dcs_write(dsi, cmd->data[0],
> > +                                                        cmd->len <= 1 ? NULL :
> > +                                                        &cmd->data[1],
> > +                                                        cmd->len - 1);
> > +                               break;
> > +                       }
> > +
> > +                       if (err < 0) {
> > +                               dev_err(panel->dev,
> > +                                       "failed to write command %u\n", i);
> > +                               return err;
> > +                       }
> > +               }
> > +       }
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_off(struct boe_panel *boe)
> > +{
> > +       struct mipi_dsi_device *dsi = boe->dsi;
> > +       int ret;
> > +
> > +       dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
> > +
> > +       ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_disable(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +
> > +       if (!boe->enabled)
> > +               return 0;
> > +
> > +       backlight_disable(boe->backlight);
> > +
> > +       boe->enabled = false;
> > +
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_unprepare(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       int ret;
> > +
> > +       if (!boe->prepared)
> > +               return 0;
> > +
> > +       ret = boe_panel_off(boe);
> > +       if (ret < 0) {
> > +               dev_err(panel->dev, "failed to set panel off: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       msleep(150);
> > +       if (boe->enable_gpio)
> > +               gpiod_set_value(boe->enable_gpio, 0);
> > +       usleep_range(500, 1000);
> > +       regulator_disable(boe->avee);
> > +       regulator_disable(boe->avdd);
> > +       usleep_range(5000, 7000);
> > +       regulator_disable(boe->pp1800);
> > +
> > +       boe->prepared = false;
> > +
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_prepare(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       int ret;
> > +
> > +       if (boe->prepared)
> > +               return 0;
> > +
> > +       if (boe->enable_gpio) {
> > +               gpiod_set_value(boe->enable_gpio, 0);
> > +               usleep_range(1000, 1500);
> > +       }
> > +
> > +       ret = regulator_enable(boe->pp1800);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       usleep_range(3000, 5000);
> > +
> > +       ret = regulator_enable(boe->avdd);
> > +       if (ret < 0)
> > +               goto poweroff1v8;
> > +       ret = regulator_enable(boe->avee);
> > +       if (ret < 0)
> > +               goto poweroffavdd;
> > +
> > +       msleep(100);
> > +
> > +       if (boe->enable_gpio) {
> > +               gpiod_set_value(boe->enable_gpio, 1);
> > +               usleep_range(10000, 12000);
> > +       }
> > +
> > +       ret = boe_panel_init(boe);
> > +       if (ret < 0) {
> > +               dev_err(panel->dev, "failed to init panel: %d\n", ret);
> > +               goto poweroff;
> > +       }
> > +
> > +       boe->prepared = true;
> > +
> > +       return 0;
> > +
> > +poweroff:
> > +       regulator_disable(boe->avee);
> > +poweroffavdd:
> > +       regulator_disable(boe->avdd);
> > +poweroff1v8:
> > +       usleep_range(5000, 7000);
> > +       regulator_disable(boe->pp1800);
> > +       if (boe->enable_gpio)
> > +               gpiod_set_value(boe->enable_gpio, 0);
> > +       return ret;
> > +}
> > +
> > +static int boe_panel_enable(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       int ret;
> > +
> > +       if (boe->enabled)
> > +               return 0;
> > +
> > +       ret = backlight_enable(boe->backlight);
> > +       if (ret) {
> > +               dev_err(panel->dev, "Failed to enable backlight %d\n",
> > +                       ret);
> > +               return ret;
> > +       }
> > +
> > +       boe->enabled = true;
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct drm_display_mode boe_default_mode = {
> > +       .clock = 159425,
> > +       .hdisplay = 1200,
> > +       .hsync_start = 1200 + 100,
> > +       .hsync_end = 1200 + 100 + 40,
> > +       .htotal = 1200 + 100 + 40 + 24,
> > +       .vdisplay = 1920,
> > +       .vsync_start = 1920 + 10,
> > +       .vsync_end = 1920 + 10 + 14,
> > +       .vtotal = 1920 + 10 + 14 + 4,
> > +       .vrefresh = 60,
> > +       .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> > +};
> > +
> > +static const struct panel_desc boe_tv101wum_nl6_desc = {
> > +       .modes = &boe_default_mode,
> > +       .bpc = 8,
> > +       .size = {
> > +               .width = 216,
> > +               .height = 135,

This is wrong, as this is a portrait panel, should be: width=135, height=216.

> > +       },
> > +       .lanes = 4,
> > +       .format = MIPI_DSI_FMT_RGB888,
> > +       .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> > +                     MIPI_DSI_MODE_LPM,
> > +       .init_cmds = boe_init_cmd,
> > +};
> > +
> > +static int boe_panel_get_modes(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       const struct drm_display_mode *m = boe->desc->modes;
> > +       struct drm_display_mode *mode;
> > +
> > +       mode = drm_mode_duplicate(panel->drm, m);
> > +       if (!mode) {
> > +               dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
> > +                       m->hdisplay, m->vdisplay, m->vrefresh);
> > +               return -ENOMEM;
> > +       }
> > +
> > +       drm_mode_set_name(mode);
> > +
>
> Sam suggested adding this here:
> mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;

Scrap that, I see that you added it in boe_default_mode.

>
> > +       drm_mode_probed_add(panel->connector, mode);
> > +
> > +       panel->connector->display_info.width_mm = boe->desc->size.width;
> > +       panel->connector->display_info.height_mm = boe->desc->size.height;
> > +       panel->connector->display_info.bpc = boe->desc->bpc;
> > +
> > +       return 1;
> > +}
> > +
> > +static const struct drm_panel_funcs boe_panel_funcs = {
> > +       .disable = boe_panel_disable,
> > +       .unprepare = boe_panel_unprepare,
> > +       .prepare = boe_panel_prepare,
> > +       .enable = boe_panel_enable,
> > +       .get_modes = boe_panel_get_modes,
> > +};
> > +
> > +static int boe_panel_add(struct boe_panel *boe)
> > +{
> > +       struct device *dev = &boe->dsi->dev;
> > +
> > +       boe->avdd = devm_regulator_get(dev, "avdd");
> > +       if (IS_ERR(boe->avdd))
> > +               return PTR_ERR(boe->avdd);
> > +
> > +       boe->avee = devm_regulator_get(dev, "avee");
> > +       if (IS_ERR(boe->avee))
> > +               return PTR_ERR(boe->avee);
> > +
> > +       boe->pp1800 = devm_regulator_get(dev, "pp1800");
> > +       if (IS_ERR(boe->pp1800))
> > +               return PTR_ERR(boe->pp1800);
> > +
> > +       boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
> > +       if (IS_ERR(boe->enable_gpio)) {
> > +               dev_err(dev, "cannot get reset-gpios %ld\n",
> > +                       PTR_ERR(boe->enable_gpio));
> > +               return PTR_ERR(boe->enable_gpio);
> > +       }
> > +
> > +       gpiod_set_value(boe->enable_gpio, 0);
> > +
> > +       boe->backlight = devm_of_find_backlight(dev);
> > +       if (IS_ERR(boe->backlight))
> > +               return PTR_ERR(boe->backlight);
> > +
> > +       drm_panel_init(&boe->base);
> > +       boe->base.funcs = &boe_panel_funcs;
> > +       boe->base.dev = &boe->dsi->dev;
> > +
> > +       return drm_panel_add(&boe->base);
> > +}
> > +
> > +static int boe_panel_probe(struct mipi_dsi_device *dsi)
> > +{
> > +       struct boe_panel *boe;
> > +       int ret;
> > +       const struct panel_desc *desc;
> > +
> > +       boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
> > +       if (!boe)
> > +               return -ENOMEM;
> > +
> > +       desc = of_device_get_match_data(&dsi->dev);
> > +       dsi->lanes = desc->lanes;
> > +       dsi->format = desc->format;
> > +       dsi->mode_flags = desc->mode_flags;
> > +       boe->desc = desc;
> > +       boe->dsi = dsi;
> > +       ret = boe_panel_add(boe);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       mipi_dsi_set_drvdata(dsi, boe);
> > +
> > +       return mipi_dsi_attach(dsi);
> > +}
> > +
> > +static int boe_panel_remove(struct mipi_dsi_device *dsi)
> > +{
> > +       struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
> > +       int ret;
> > +
> > +       ret = boe_panel_disable(&boe->base);
> > +       if (ret < 0)
> > +               dev_err(&dsi->dev, "failed to disable panel: %d\n", ret);
> > +
> > +       ret = mipi_dsi_detach(dsi);
> > +       if (ret < 0)
> > +               dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
> > +
> > +       if (boe->base.dev)
> > +               drm_panel_remove(&boe->base);
> > +
> > +       return 0;
> > +}
> > +
> > +static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
> > +{
> > +       struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
> > +
> > +       boe_panel_disable(&boe->base);
> > +}
> > +
> > +static const struct of_device_id boe_of_match[] = {
> > +       { .compatible = "boe,tv101wum-nl6",
> > +         .data = &boe_tv101wum_nl6_desc
> > +       },
> > +       { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, boe_of_match);
> > +
> > +static struct mipi_dsi_driver boe_panel_driver = {
> > +       .driver = {
> > +               .name = "panel-boe-tv101wum-nl6",
> > +               .of_match_table = boe_of_match,
> > +       },
> > +       .probe = boe_panel_probe,
> > +       .remove = boe_panel_remove,
> > +       .shutdown = boe_panel_shutdown,
> > +};
> > +module_mipi_dsi_driver(boe_panel_driver);
> > +
> > +MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
> > +MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.21.0
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Nicolas Boichat <drinkcat@chromium.org>
Subject: Re: [v2 2/2] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video
 mode panel
Date: Tue, 25 Jun 2019 08:42:16 +0800
Message-ID: <CANMq1KBS0DhVcM=EMqNQfMuh91WJ-Vk5EZvVKkLQQq2VECjraA@mail.gmail.com>
References: <20190624060343.62451-1-jitao.shi@mediatek.com>
 <20190624060343.62451-3-jitao.shi@mediatek.com>
 <CANMq1KABzuKu1nyP4Mq-6eHPA3tFZ+AViAaouzrgHu9RL4i-6A@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Return-path: <dri-devel-bounces@lists.freedesktop.org>
In-Reply-To: <CANMq1KABzuKu1nyP4Mq-6eHPA3tFZ+AViAaouzrgHu9RL4i-6A@mail.gmail.com>
List-Unsubscribe: <https://lists.freedesktop.org/mailman/options/dri-devel>,
 <mailto:dri-devel-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <https://lists.freedesktop.org/archives/dri-devel>
List-Post: <mailto:dri-devel@lists.freedesktop.org>
List-Help: <mailto:dri-devel-request@lists.freedesktop.org?subject=help>
List-Subscribe: <https://lists.freedesktop.org/mailman/listinfo/dri-devel>,
 <mailto:dri-devel-request@lists.freedesktop.org?subject=subscribe>
Errors-To: dri-devel-bounces@lists.freedesktop.org
Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
To: Jitao Shi <jitao.shi@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, David Airlie <airlied@linux.ie>, stonea168@163.com, dri-devel@lists.freedesktop.org, Ajay Kumar <ajaykumar.rs@samsung.com>, Vincent Palatin <vpalatin@chromium.org>, cawa cheng <cawa.cheng@mediatek.com>, Yingjoe Chen <yingjoe.chen@mediatek.com>, Thierry Reding <treding@nvidia.com>, Sean Paul <seanpaul@chromium.org>, linux-pwm@vger.kernel.org, Pawel Moll <pawel.moll@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Rob Herring <robh+dt@kernel.org>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@lists.infradead.org>, Russell King <rmk+kernel@arm.linux.org.uk>, Matthias Brugger <matthias.bgg@gmail.com>, Eddie Huang <eddie.huang@mediatek.com>, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>, Rahul Sharma <rahul.sharma@samsung.com>, srv_heupstream <srv_heupstream@mediatek.com>, lk
List-Id: devicetree@vger.kernel.org

T24gTW9uLCBKdW4gMjQsIDIwMTkgYXQgNDoyNSBQTSBOaWNvbGFzIEJvaWNoYXQgPGRyaW5rY2F0
QGNocm9taXVtLm9yZz4gd3JvdGU6Cj4KPiBPbiBNb24sIEp1biAyNCwgMjAxOSBhdCAyOjA0IFBN
IEppdGFvIFNoaSA8aml0YW8uc2hpQG1lZGlhdGVrLmNvbT4gd3JvdGU6Cj4gPgo+ID4gQWRkIGRy
aXZlciBmb3IgQk9FIHR2MTAxd3VtLW5sNiBwYW5lbCBpcyBhIDEwLjEiIDEyMDB4MTkyMCBwYW5l
bC4KPiA+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBKaXRhbyBTaGkgPGppdGFvLnNoaUBtZWRpYXRlay5j
b20+Cj4gPiAtLS0KPiA+ICBkcml2ZXJzL2dwdS9kcm0vcGFuZWwvS2NvbmZpZyAgICAgICAgICAg
ICAgICAgfCAgMTAgKwo+ID4gIGRyaXZlcnMvZ3B1L2RybS9wYW5lbC9NYWtlZmlsZSAgICAgICAg
ICAgICAgICB8ICAgMSArCj4gPiAgLi4uL2dwdS9kcm0vcGFuZWwvcGFuZWwtYm9lLXR2MTAxd3Vt
LW5sNi5jICAgIHwgNzE1ICsrKysrKysrKysrKysrKysrKwo+ID4gIDMgZmlsZXMgY2hhbmdlZCwg
NzI2IGluc2VydGlvbnMoKykKPiA+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9ncHUvZHJt
L3BhbmVsL3BhbmVsLWJvZS10djEwMXd1bS1ubDYuYwo+ID4KPiA+IGRpZmYgLS1naXQgYS9kcml2
ZXJzL2dwdS9kcm0vcGFuZWwvS2NvbmZpZyBiL2RyaXZlcnMvZ3B1L2RybS9wYW5lbC9LY29uZmln
Cj4gPiBpbmRleCBlMzZkYmI0ZGY4NjcuLjJiMDU1Y2UwNzAwYiAxMDA2NDQKPiA+IC0tLSBhL2Ry
aXZlcnMvZ3B1L2RybS9wYW5lbC9LY29uZmlnCj4gPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vcGFu
ZWwvS2NvbmZpZwo+ID4gQEAgLTE3LDYgKzE3LDE1IEBAIGNvbmZpZyBEUk1fUEFORUxfQVJNX1ZF
UlNBVElMRQo+ID4gICAgICAgICAgIHJlZmVyZW5jZSBkZXNpZ25zLiBUaGUgcGFuZWwgaXMgZGV0
ZWN0ZWQgdXNpbmcgc3BlY2lhbCByZWdpc3RlcnMKPiA+ICAgICAgICAgICBpbiB0aGUgVmVyc2F0
aWxlIGZhbWlseSBzeXNjb24gcmVnaXN0ZXJzLgo+ID4KPiA+ICtjb25maWcgRFJNX1BBTkVMX0JP
RV9UVjEwMVdVTV9OTDYKPiA+ICsgICAgICAgdHJpc3RhdGUgIkJPRSBUVjEwMVdVTSAxMjAweDE5
MjAgcGFuZWwiCj4gPiArICAgICAgIGRlcGVuZHMgb24gT0YKPiA+ICsgICAgICAgZGVwZW5kcyBv
biBEUk1fTUlQSV9EU0kKPiA+ICsgICAgICAgZGVwZW5kcyBvbiBCQUNLTElHSFRfQ0xBU1NfREVW
SUNFCj4gPiArICAgICAgIGhlbHAKPiA+ICsgICAgICAgICBTYXkgWSBoZXJlIGlmIHlvdSB3YW50
IHRvIHN1cHBvcnQgZm9yIEJPRSBUVjEwMVdVTSBXVVhHQSBQQU5FTAo+ID4gKyAgICAgICAgIERT
SSBWaWRlbyBNb2RlIHBhbmVsCj4gPiArCj4gPiAgY29uZmlnIERSTV9QQU5FTF9MVkRTCj4gPiAg
ICAgICAgIHRyaXN0YXRlICJHZW5lcmljIExWRFMgcGFuZWwgZHJpdmVyIgo+ID4gICAgICAgICBk
ZXBlbmRzIG9uIE9GCj4gPiBAQCAtMjcyLDQgKzI4MSw1IEBAIGNvbmZpZyBEUk1fUEFORUxfVFJV
TFlfTlQzNTU5N19XUVhHQQo+ID4gICAgICAgICBoZWxwCj4gPiAgICAgICAgICAgU2F5IFkgaGVy
ZSBpZiB5b3Ugd2FudCB0byBlbmFibGUgc3VwcG9ydCBmb3IgVHJ1bHkgTlQzNTU5NyBXUVhHQSBE
dWFsIERTSQo+ID4gICAgICAgICAgIFZpZGVvIE1vZGUgcGFuZWwKPiA+ICsKPgo+IERyb3AgdGhp
cyBjaGFuZ2UuCj4KPiA+ICBlbmRtZW51Cj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJt
L3BhbmVsL01ha2VmaWxlIGIvZHJpdmVycy9ncHUvZHJtL3BhbmVsL01ha2VmaWxlCj4gPiBpbmRl
eCA3OGUzZGMzNzZiZGQuLjhkMDA5MjIzYzQ0ZSAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZ3B1
L2RybS9wYW5lbC9NYWtlZmlsZQo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3BhbmVsL01ha2Vm
aWxlCj4gPiBAQCAtMSw1ICsxLDYgQEAKPiA+ICAjIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBH
UEwtMi4wCj4gPiAgb2JqLSQoQ09ORklHX0RSTV9QQU5FTF9BUk1fVkVSU0FUSUxFKSArPSBwYW5l
bC1hcm0tdmVyc2F0aWxlLm8KPiA+ICtvYmotJChDT05GSUdfRFJNX1BBTkVMX0JPRV9UVjEwMVdV
TV9OTDYpICs9IHBhbmVsLWJvZS10djEwMXd1bS1ubDYubwo+ID4gIG9iai0kKENPTkZJR19EUk1f
UEFORUxfTFZEUykgKz0gcGFuZWwtbHZkcy5vCj4gPiAgb2JqLSQoQ09ORklHX0RSTV9QQU5FTF9T
SU1QTEUpICs9IHBhbmVsLXNpbXBsZS5vCj4gPiAgb2JqLSQoQ09ORklHX0RSTV9QQU5FTF9GRUlZ
QU5HX0ZZMDcwMjRESTI2QTMwRCkgKz0gcGFuZWwtZmVpeWFuZy1meTA3MDI0ZGkyNmEzMGQubwo+
ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9wYW5lbC9wYW5lbC1ib2UtdHYxMDF3dW0t
bmw2LmMgYi9kcml2ZXJzL2dwdS9kcm0vcGFuZWwvcGFuZWwtYm9lLXR2MTAxd3VtLW5sNi5jCj4g
PiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+ID4gaW5kZXggMDAwMDAwMDAwMDAwLi42ZTA2Yzg1MDY2
MjMKPiA+IC0tLSAvZGV2L251bGwKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9wYW5lbC9wYW5l
bC1ib2UtdHYxMDF3dW0tbmw2LmMKPiA+IEBAIC0wLDAgKzEsNzE1IEBACj4gPiArLy8gU1BEWC1M
aWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAKPiA+ICsvKgo+ID4gKyAqIENvcHlyaWdodCAoYykg
MjAxOCBNZWRpYVRlayBJbmMuCj4gPiArICogQXV0aG9yOiBKaXRhbyBTaGkgPGppdGFvLnNoaUBt
ZWRpYXRlay5jb20+Cj4gPiArICovCj4gPiArCj4gPiArI2luY2x1ZGUgPGxpbnV4L2JhY2tsaWdo
dC5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9kZWxheS5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9n
cGlvL2NvbnN1bWVyLmg+Cj4gPiArI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPgo+ID4gKyNpbmNs
dWRlIDxsaW51eC9vZi5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4KPiA+ICsj
aW5jbHVkZSA8bGludXgvcmVndWxhdG9yL2NvbnN1bWVyLmg+Cj4gPiArCj4gPiArI2luY2x1ZGUg
PGRybS9kcm1fY3J0Yy5oPgo+ID4gKyNpbmNsdWRlIDxkcm0vZHJtX21pcGlfZHNpLmg+Cj4gPiAr
I2luY2x1ZGUgPGRybS9kcm1fcGFuZWwuaD4KPiA+ICsKPiA+ICsjaW5jbHVkZSA8dmlkZW8vbWlw
aV9kaXNwbGF5Lmg+Cj4gPiArCj4gPiArc3RydWN0IHBhbmVsX2Rlc2Mgewo+ID4gKyAgICAgICBj
b25zdCBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZXM7Cj4gPiArICAgICAgIHVuc2lnbmVk
IGludCBicGM7Cj4gPiArCj4gPiArICAgICAgIC8qKgo+ID4gKyAgICAgICAgKiBAd2lkdGg6IHdp
ZHRoIChpbiBtaWxsaW1ldGVycykgb2YgdGhlIHBhbmVsJ3MgYWN0aXZlIGRpc3BsYXkgYXJlYQo+
ID4gKyAgICAgICAgKiBAaGVpZ2h0OiBoZWlnaHQgKGluIG1pbGxpbWV0ZXJzKSBvZiB0aGUgcGFu
ZWwncyBhY3RpdmUgZGlzcGxheSBhcmVhCj4gPiArICAgICAgICAqLwo+ID4gKyAgICAgICBzdHJ1
Y3Qgewo+ID4gKyAgICAgICAgICAgICAgIHVuc2lnbmVkIGludCB3aWR0aDsKPiA+ICsgICAgICAg
ICAgICAgICB1bnNpZ25lZCBpbnQgaGVpZ2h0Owo+ID4gKyAgICAgICB9IHNpemU7Cj4gPiArCj4g
PiArICAgICAgIHVuc2lnbmVkIGxvbmcgbW9kZV9mbGFnczsKPiA+ICsgICAgICAgZW51bSBtaXBp
X2RzaV9waXhlbF9mb3JtYXQgZm9ybWF0Owo+ID4gKyAgICAgICBjb25zdCBzdHJ1Y3QgcGFuZWxf
aW5pdF9jbWQgKmluaXRfY21kczsKPiA+ICsgICAgICAgdW5zaWduZWQgaW50IGxhbmVzOwo+ID4g
K307Cj4gPiArCj4gPiArc3RydWN0IGJvZV9wYW5lbCB7Cj4gPiArICAgICAgIHN0cnVjdCBkcm1f
cGFuZWwgYmFzZTsKPiA+ICsgICAgICAgc3RydWN0IG1pcGlfZHNpX2RldmljZSAqZHNpOwo+ID4g
Kwo+ID4gKyAgICAgICBjb25zdCBzdHJ1Y3QgcGFuZWxfZGVzYyAqZGVzYzsKPiA+ICsKPiA+ICsg
ICAgICAgc3RydWN0IGJhY2tsaWdodF9kZXZpY2UgKmJhY2tsaWdodDsKPiA+ICsgICAgICAgc3Ry
dWN0IHJlZ3VsYXRvciAqcHAxODAwOwo+ID4gKyAgICAgICBzdHJ1Y3QgcmVndWxhdG9yICphdmVl
Owo+ID4gKyAgICAgICBzdHJ1Y3QgcmVndWxhdG9yICphdmRkOwo+ID4gKyAgICAgICBzdHJ1Y3Qg
Z3Bpb19kZXNjICplbmFibGVfZ3BpbzsKPiA+ICsKPiA+ICsgICAgICAgYm9vbCBwcmVwYXJlZDsK
PiA+ICsgICAgICAgYm9vbCBlbmFibGVkOwo+ID4gKwo+ID4gKyAgICAgICBjb25zdCBzdHJ1Y3Qg
ZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZTsKPiA+ICt9Owo+ID4gKwo+ID4gK2VudW0gZHNpX2NtZF90
eXBlIHsKPiA+ICsgICAgICAgSU5JVF9EQ1NfQ01ELAo+ID4gKyAgICAgICBERUxBWV9DTUQsCj4g
PiArfTsKPiA+ICsKPiA+ICtzdHJ1Y3QgcGFuZWxfaW5pdF9jbWQgewo+ID4gKyAgICAgICBlbnVt
IGRzaV9jbWRfdHlwZSB0eXBlOwo+ID4gKyAgICAgICBzaXplX3QgbGVuOwo+ID4gKyAgICAgICBj
b25zdCBjaGFyICpkYXRhOwo+ID4gK307Cj4gPiArCj4gPiArI2RlZmluZSBfSU5JVF9EQ1NfQ01E
KC4uLikgeyBcCj4gPiArICAgICAgIC50eXBlID0gSU5JVF9EQ1NfQ01ELCBcCj4gPiArICAgICAg
IC5sZW4gPSBzaXplb2YoKGNoYXJbXSl7X19WQV9BUkdTX199KSwgXAo+ID4gKyAgICAgICAuZGF0
YSA9IChjaGFyW10pe19fVkFfQVJHU19ffSB9Cj4gPiArCj4gPiArI2RlZmluZSBfSU5JVF9ERUxB
WV9DTUQoLi4uKSB7IFwKPiA+ICsgICAgICAgLnR5cGUgPSBERUxBWV9DTUQsXAo+ID4gKyAgICAg
ICAubGVuID0gc2l6ZW9mKChjaGFyW10pe19fVkFfQVJHU19ffSksIFwKPiA+ICsgICAgICAgLmRh
dGEgPSAoY2hhcltdKXtfX1ZBX0FSR1NfX30gfQo+ID4gKwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1
Y3QgcGFuZWxfaW5pdF9jbWQgYm9lX2luaXRfY21kW10gPSB7Cj4gPiArICAgICAgIF9JTklUX0RF
TEFZX0NNRCgyNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwNSksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhCMSwgMHhFNSksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhCMywgMHg1MiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwMCksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMywgMHg4OCksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhCMCwgMHgwNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOCwgMHgwMCks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwMCksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhCNiwgMHgwMyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQSwgMHg4
QiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRiwgMHgxQSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDMCwgMHgwRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMiwg
MHgwQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMywgMHgwMiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDNCwgMHgwQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
NSwgMHgwMiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwMSksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhFMCwgMHgyNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhFMSwgMHgyNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEQywgMHgwMCksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhERCwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhDQywgMHgyNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRCwgMHgyNiksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOCwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhDOSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEMiwgMHgwMyks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEMywgMHgwMyksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhFNiwgMHgwNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhFNywgMHgw
NCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNCwgMHgwOSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDNSwgMHgwOSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEOCwg
MHgwQSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEOSwgMHgwQSksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDMiwgMHgwQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
MywgMHgwQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhENiwgMHgwQyksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhENywgMHgwQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhDMCwgMHgwNSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMSwgMHgwNSksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhENCwgMHgwNiksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhENSwgMHgwNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQSwgMHgwNyksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQiwgMHgwNyksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhERSwgMHgwOCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhERiwgMHgwOCks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwMiksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhDMCwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMSwgMHgw
RCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMiwgMHgxNyksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDMywgMHgyNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNCwg
MHgzMSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNSwgMHgxQyksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDNiwgMHgyQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
NywgMHgzMyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOCwgMHgzMSksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhDOSwgMHgzNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhDQSwgMHgzNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQiwgMHgzNyksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhDQywgMHgzOSksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhDRCwgMHgyRSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRSwgMHgyRiksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRiwgMHgyRiksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhEMCwgMHgwNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEMiwgMHgwMCks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEMywgMHgwRCksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhENCwgMHgxNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhENSwgMHgy
NiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhENiwgMHgzMSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhENywgMHgzRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEOCwg
MHgzRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEOSwgMHgzRiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhEQSwgMHgzRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhE
QiwgMHgzNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhEQywgMHgzNyksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhERCwgMHgzNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhERSwgMHgzOSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhERiwgMHgyRSksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhFMCwgMHgyRiksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhFMSwgMHgyRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhFMiwgMHgwNyksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwMyksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhDOCwgMHgwQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOSwgMHgwNyks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMywgMHgwMCksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhFNywgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNSwgMHgy
QSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhERSwgMHgyQSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDQSwgMHg0MyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOSwg
MHgwNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhFNCwgMHhDMCksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhFNSwgMHgwRCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
QiwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwNiksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhCOCwgMHhBNSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhDMCwgMHhBNSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNywgMHgwRiksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhENSwgMHgzMiksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhCOCwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMCwgMHgwMCksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQywgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhCMCwgMHgwNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMSwgMHgwMCks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMiwgMHgwMiksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhCMywgMHgwRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNCwgMHgy
NSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNSwgMHgzOSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhCNiwgMHg0RSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNywg
MHg3MiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOCwgMHg5NyksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhCOSwgMHhEQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhC
QSwgMHgyMiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQiwgMHhBNCksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhCQywgMHgyQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhCRCwgMHgyRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRSwgMHhBOSksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhCRiwgMHgyNSksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhDMCwgMHg2MSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMSwgMHg5NyksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMiwgMHhCMiksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhDMywgMHhDRCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNCwgMHhEOSks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNSwgMHhFNyksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhDNiwgMHhGNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNywgMHhG
QSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOCwgMHhGQyksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDOSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQSwg
MHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQiwgMHgxNiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDQywgMHhBRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
RCwgMHhGRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRSwgMHhGRiksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwOCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhCMSwgMHgwNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMiwgMHgwNSksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhCMywgMHgxMSksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhCNCwgMHgyNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNSwgMHgzOSksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNiwgMHg0RiksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhCNywgMHg3MiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOCwgMHg5OCks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOSwgMHhEQyksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhCQSwgMHgyMyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQiwgMHhB
NiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQywgMHgyQyksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhCRCwgMHgzMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRSwg
MHhBQSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRiwgMHgyNiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDMCwgMHg2MiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
MSwgMHg5QiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMiwgMHhCNSksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhDMywgMHhDRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhDNCwgMHhEQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNSwgMHhFOCksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhDNiwgMHhGNSksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhDNywgMHhGQSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOCwgMHhGQyksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhDQSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQiwgMHgxNiks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQywgMHhBRiksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhDRCwgMHhGRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRSwgMHhG
RiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwOSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhCMSwgMHgwNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMiwg
MHgwMiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMywgMHgxNiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhCNCwgMHgyNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhC
NSwgMHgzQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNiwgMHg0RiksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhCNywgMHg3MyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhCOCwgMHg5OSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOSwgMHhFMCksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhCQSwgMHgyNiksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhCQiwgMHhBRCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQywgMHgzNiksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRCwgMHgzQSksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhCRSwgMHhBRSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRiwgMHgyQSks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMCwgMHg2NiksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhDMSwgMHg5RSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMiwgMHhC
OCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMywgMHhEMSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDNCwgMHhERCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNSwg
MHhFOSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNiwgMHhGNiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDNywgMHhGQSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
OCwgMHhGQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOSwgMHgwMCksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhDQSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhDQiwgMHgxNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQywgMHhBRiksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhDRCwgMHhGRiksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhDRSwgMHhGRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwQSksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhCMiwgMHgwMiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMywgMHgwRiks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNCwgMHgyNSksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhCNSwgMHgzOSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNiwgMHg0
RSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNywgMHg3MiksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhCOCwgMHg5NyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOSwg
MHhEQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQSwgMHgyMiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhCQiwgMHhBNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhC
QywgMHgyQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRCwgMHgyRiksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhCRSwgMHhBOSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhCRiwgMHgyNSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMCwgMHg2MSksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhDMSwgMHg5NyksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhDMiwgMHhCMiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMywgMHhDRCksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNCwgMHhEOSksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhDNSwgMHhFNyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNiwgMHhGNCks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNywgMHhGQSksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhDOCwgMHhGQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOSwgMHgw
MCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQSwgMHgwMCksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDQiwgMHgxNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQywg
MHhBRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRCwgMHhGRiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDRSwgMHhGRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhC
MCwgMHgwQiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMSwgMHgwNCksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhCMiwgMHgwNSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhCMywgMHgxMSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNCwgMHgyNCksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhCNSwgMHgzOSksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhCNiwgMHg0RiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNywgMHg3MiksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOCwgMHg5OCksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhCOSwgMHhEQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQSwgMHgyMyks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQiwgMHhBNiksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhCQywgMHgyQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRCwgMHgz
MCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRSwgMHhBQSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhCRiwgMHgyNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMCwg
MHg2MiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMSwgMHg5QiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDMiwgMHhCNSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
MywgMHhDRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNCwgMHhEQiksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhDNSwgMHhFOCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhDNiwgMHhGNSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNywgMHhGQSksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhDOCwgMHhGQyksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhDOSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQSwgMHgwMCksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQiwgMHgxNiksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhDQywgMHhBRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRCwgMHhGRiks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRSwgMHhGRiksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhCMCwgMHgwQyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMSwgMHgw
NCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMiwgMHgwMiksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhCMywgMHgxNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNCwg
MHgyNCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCNSwgMHgzQiksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhCNiwgMHg0RiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhC
NywgMHg3MyksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOCwgMHg5OSksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhCOSwgMHhFMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhCQSwgMHgyNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCQiwgMHhBRCksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhCQywgMHgzNiksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhCRCwgMHgzQSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRSwgMHhBRSksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCRiwgMHgyQSksCj4gPiArICAgICAgIF9JTklUX0RD
U19DTUQoMHhDMCwgMHg2NiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMSwgMHg5RSks
Cj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDMiwgMHhCOCksCj4gPiArICAgICAgIF9JTklU
X0RDU19DTUQoMHhDMywgMHhEMSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNCwgMHhE
RCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNSwgMHhFOSksCj4gPiArICAgICAgIF9J
TklUX0RDU19DTUQoMHhDNiwgMHhGNiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDNywg
MHhGQSksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDOCwgMHhGQyksCj4gPiArICAgICAg
IF9JTklUX0RDU19DTUQoMHhDOSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhD
QSwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDQiwgMHgxNiksCj4gPiArICAg
ICAgIF9JTklUX0RDU19DTUQoMHhDQywgMHhBRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQo
MHhDRCwgMHhGRiksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhDRSwgMHhGRiksCj4gPiAr
ICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwMCksCj4gPiArICAgICAgIF9JTklUX0RDU19D
TUQoMHhCMywgMHgwOCksCj4gPiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCMCwgMHgwNCksCj4g
PiArICAgICAgIF9JTklUX0RDU19DTUQoMHhCOCwgMHg2OCksCj4gPiArICAgICAgIF9JTklUX0RF
TEFZX0NNRCgxNTApLAo+ID4gKyAgICAgICB7fSwKPiA+ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBp
bmxpbmUgc3RydWN0IGJvZV9wYW5lbCAqdG9fYm9lX3BhbmVsKHN0cnVjdCBkcm1fcGFuZWwgKnBh
bmVsKQo+ID4gK3sKPiA+ICsgICAgICAgcmV0dXJuIGNvbnRhaW5lcl9vZihwYW5lbCwgc3RydWN0
IGJvZV9wYW5lbCwgYmFzZSk7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbnQgYm9lX3BhbmVs
X2luaXQoc3RydWN0IGJvZV9wYW5lbCAqYm9lKQo+ID4gK3sKPiA+ICsgICAgICAgc3RydWN0IG1p
cGlfZHNpX2RldmljZSAqZHNpID0gYm9lLT5kc2k7Cj4gPiArICAgICAgIHN0cnVjdCBkcm1fcGFu
ZWwgKnBhbmVsID0gJmJvZS0+YmFzZTsKPiA+ICsgICAgICAgaW50IGVyciwgaTsKPiA+ICsKPiA+
ICsgICAgICAgaWYgKGJvZS0+ZGVzYy0+aW5pdF9jbWRzKSB7Cj4gPiArICAgICAgICAgICAgICAg
Y29uc3Qgc3RydWN0IHBhbmVsX2luaXRfY21kICppbml0X2NtZHMgPSBib2UtPmRlc2MtPmluaXRf
Y21kczsKPiA+ICsKPiA+ICsgICAgICAgICAgICAgICBmb3IgKGkgPSAwOyBpbml0X2NtZHNbaV0u
bGVuICE9IDA7IGkrKykgewo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgY29uc3Qgc3RydWN0
IHBhbmVsX2luaXRfY21kICpjbWQgPSAmaW5pdF9jbWRzW2ldOwo+ID4gKwo+ID4gKyAgICAgICAg
ICAgICAgICAgICAgICAgc3dpdGNoIChjbWQtPnR5cGUpIHsKPiA+ICsgICAgICAgICAgICAgICAg
ICAgICAgIGNhc2UgREVMQVlfQ01EOgo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICBtc2xlZXAoY21kLT5kYXRhWzBdKTsKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgZXJyID0gMDsKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgYnJlYWs7Cj4g
PiArCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBjYXNlIElOSVRfRENTX0NNRDoKPiA+ICsg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZXJyID0gbWlwaV9kc2lfZGNzX3dyaXRlKGRz
aSwgY21kLT5kYXRhWzBdLAo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgY21kLT5sZW4gPD0gMSA/IE5VTEwgOgo+ID4gKyAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgJmNtZC0+ZGF0
YVsxXSwKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgIGNtZC0+bGVuIC0gMSk7Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgIGJyZWFrOwo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgfQo+ID4gKwo+ID4gKyAgICAg
ICAgICAgICAgICAgICAgICAgaWYgKGVyciA8IDApIHsKPiA+ICsgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgZGV2X2VycihwYW5lbC0+ZGV2LAo+ID4gKyAgICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICJmYWlsZWQgdG8gd3JpdGUgY29tbWFuZCAldVxuIiwgaSk7Cj4g
PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJldHVybiBlcnI7Cj4gPiArICAgICAg
ICAgICAgICAgICAgICAgICB9Cj4gPiArICAgICAgICAgICAgICAgfQo+ID4gKyAgICAgICB9Cj4g
PiArICAgICAgIHJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IGJvZV9wYW5l
bF9vZmYoc3RydWN0IGJvZV9wYW5lbCAqYm9lKQo+ID4gK3sKPiA+ICsgICAgICAgc3RydWN0IG1p
cGlfZHNpX2RldmljZSAqZHNpID0gYm9lLT5kc2k7Cj4gPiArICAgICAgIGludCByZXQ7Cj4gPiAr
Cj4gPiArICAgICAgIGRzaS0+bW9kZV9mbGFncyAmPSB+TUlQSV9EU0lfTU9ERV9MUE07Cj4gPiAr
Cj4gPiArICAgICAgIHJldCA9IG1pcGlfZHNpX2Rjc19lbnRlcl9zbGVlcF9tb2RlKGRzaSk7Cj4g
PiArICAgICAgIGlmIChyZXQgPCAwKQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiByZXQ7Cj4g
PiArCj4gPiArICAgICAgIHJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IGJv
ZV9wYW5lbF9kaXNhYmxlKHN0cnVjdCBkcm1fcGFuZWwgKnBhbmVsKQo+ID4gK3sKPiA+ICsgICAg
ICAgc3RydWN0IGJvZV9wYW5lbCAqYm9lID0gdG9fYm9lX3BhbmVsKHBhbmVsKTsKPiA+ICsKPiA+
ICsgICAgICAgaWYgKCFib2UtPmVuYWJsZWQpCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIDA7
Cj4gPiArCj4gPiArICAgICAgIGJhY2tsaWdodF9kaXNhYmxlKGJvZS0+YmFja2xpZ2h0KTsKPiA+
ICsKPiA+ICsgICAgICAgYm9lLT5lbmFibGVkID0gZmFsc2U7Cj4gPiArCj4gPiArICAgICAgIHJl
dHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IGJvZV9wYW5lbF91bnByZXBhcmUo
c3RydWN0IGRybV9wYW5lbCAqcGFuZWwpCj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3QgYm9lX3Bh
bmVsICpib2UgPSB0b19ib2VfcGFuZWwocGFuZWwpOwo+ID4gKyAgICAgICBpbnQgcmV0Owo+ID4g
Kwo+ID4gKyAgICAgICBpZiAoIWJvZS0+cHJlcGFyZWQpCj4gPiArICAgICAgICAgICAgICAgcmV0
dXJuIDA7Cj4gPiArCj4gPiArICAgICAgIHJldCA9IGJvZV9wYW5lbF9vZmYoYm9lKTsKPiA+ICsg
ICAgICAgaWYgKHJldCA8IDApIHsKPiA+ICsgICAgICAgICAgICAgICBkZXZfZXJyKHBhbmVsLT5k
ZXYsICJmYWlsZWQgdG8gc2V0IHBhbmVsIG9mZjogJWRcbiIsIHJldCk7Cj4gPiArICAgICAgICAg
ICAgICAgcmV0dXJuIHJldDsKPiA+ICsgICAgICAgfQo+ID4gKwo+ID4gKyAgICAgICBtc2xlZXAo
MTUwKTsKPiA+ICsgICAgICAgaWYgKGJvZS0+ZW5hYmxlX2dwaW8pCj4gPiArICAgICAgICAgICAg
ICAgZ3Bpb2Rfc2V0X3ZhbHVlKGJvZS0+ZW5hYmxlX2dwaW8sIDApOwo+ID4gKyAgICAgICB1c2xl
ZXBfcmFuZ2UoNTAwLCAxMDAwKTsKPiA+ICsgICAgICAgcmVndWxhdG9yX2Rpc2FibGUoYm9lLT5h
dmVlKTsKPiA+ICsgICAgICAgcmVndWxhdG9yX2Rpc2FibGUoYm9lLT5hdmRkKTsKPiA+ICsgICAg
ICAgdXNsZWVwX3JhbmdlKDUwMDAsIDcwMDApOwo+ID4gKyAgICAgICByZWd1bGF0b3JfZGlzYWJs
ZShib2UtPnBwMTgwMCk7Cj4gPiArCj4gPiArICAgICAgIGJvZS0+cHJlcGFyZWQgPSBmYWxzZTsK
PiA+ICsKPiA+ICsgICAgICAgcmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbnQg
Ym9lX3BhbmVsX3ByZXBhcmUoc3RydWN0IGRybV9wYW5lbCAqcGFuZWwpCj4gPiArewo+ID4gKyAg
ICAgICBzdHJ1Y3QgYm9lX3BhbmVsICpib2UgPSB0b19ib2VfcGFuZWwocGFuZWwpOwo+ID4gKyAg
ICAgICBpbnQgcmV0Owo+ID4gKwo+ID4gKyAgICAgICBpZiAoYm9lLT5wcmVwYXJlZCkKPiA+ICsg
ICAgICAgICAgICAgICByZXR1cm4gMDsKPiA+ICsKPiA+ICsgICAgICAgaWYgKGJvZS0+ZW5hYmxl
X2dwaW8pIHsKPiA+ICsgICAgICAgICAgICAgICBncGlvZF9zZXRfdmFsdWUoYm9lLT5lbmFibGVf
Z3BpbywgMCk7Cj4gPiArICAgICAgICAgICAgICAgdXNsZWVwX3JhbmdlKDEwMDAsIDE1MDApOwo+
ID4gKyAgICAgICB9Cj4gPiArCj4gPiArICAgICAgIHJldCA9IHJlZ3VsYXRvcl9lbmFibGUoYm9l
LT5wcDE4MDApOwo+ID4gKyAgICAgICBpZiAocmV0IDwgMCkKPiA+ICsgICAgICAgICAgICAgICBy
ZXR1cm4gcmV0Owo+ID4gKwo+ID4gKyAgICAgICB1c2xlZXBfcmFuZ2UoMzAwMCwgNTAwMCk7Cj4g
PiArCj4gPiArICAgICAgIHJldCA9IHJlZ3VsYXRvcl9lbmFibGUoYm9lLT5hdmRkKTsKPiA+ICsg
ICAgICAgaWYgKHJldCA8IDApCj4gPiArICAgICAgICAgICAgICAgZ290byBwb3dlcm9mZjF2ODsK
PiA+ICsgICAgICAgcmV0ID0gcmVndWxhdG9yX2VuYWJsZShib2UtPmF2ZWUpOwo+ID4gKyAgICAg
ICBpZiAocmV0IDwgMCkKPiA+ICsgICAgICAgICAgICAgICBnb3RvIHBvd2Vyb2ZmYXZkZDsKPiA+
ICsKPiA+ICsgICAgICAgbXNsZWVwKDEwMCk7Cj4gPiArCj4gPiArICAgICAgIGlmIChib2UtPmVu
YWJsZV9ncGlvKSB7Cj4gPiArICAgICAgICAgICAgICAgZ3Bpb2Rfc2V0X3ZhbHVlKGJvZS0+ZW5h
YmxlX2dwaW8sIDEpOwo+ID4gKyAgICAgICAgICAgICAgIHVzbGVlcF9yYW5nZSgxMDAwMCwgMTIw
MDApOwo+ID4gKyAgICAgICB9Cj4gPiArCj4gPiArICAgICAgIHJldCA9IGJvZV9wYW5lbF9pbml0
KGJvZSk7Cj4gPiArICAgICAgIGlmIChyZXQgPCAwKSB7Cj4gPiArICAgICAgICAgICAgICAgZGV2
X2VycihwYW5lbC0+ZGV2LCAiZmFpbGVkIHRvIGluaXQgcGFuZWw6ICVkXG4iLCByZXQpOwo+ID4g
KyAgICAgICAgICAgICAgIGdvdG8gcG93ZXJvZmY7Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsg
ICAgICAgYm9lLT5wcmVwYXJlZCA9IHRydWU7Cj4gPiArCj4gPiArICAgICAgIHJldHVybiAwOwo+
ID4gKwo+ID4gK3Bvd2Vyb2ZmOgo+ID4gKyAgICAgICByZWd1bGF0b3JfZGlzYWJsZShib2UtPmF2
ZWUpOwo+ID4gK3Bvd2Vyb2ZmYXZkZDoKPiA+ICsgICAgICAgcmVndWxhdG9yX2Rpc2FibGUoYm9l
LT5hdmRkKTsKPiA+ICtwb3dlcm9mZjF2ODoKPiA+ICsgICAgICAgdXNsZWVwX3JhbmdlKDUwMDAs
IDcwMDApOwo+ID4gKyAgICAgICByZWd1bGF0b3JfZGlzYWJsZShib2UtPnBwMTgwMCk7Cj4gPiAr
ICAgICAgIGlmIChib2UtPmVuYWJsZV9ncGlvKQo+ID4gKyAgICAgICAgICAgICAgIGdwaW9kX3Nl
dF92YWx1ZShib2UtPmVuYWJsZV9ncGlvLCAwKTsKPiA+ICsgICAgICAgcmV0dXJuIHJldDsKPiA+
ICt9Cj4gPiArCj4gPiArc3RhdGljIGludCBib2VfcGFuZWxfZW5hYmxlKHN0cnVjdCBkcm1fcGFu
ZWwgKnBhbmVsKQo+ID4gK3sKPiA+ICsgICAgICAgc3RydWN0IGJvZV9wYW5lbCAqYm9lID0gdG9f
Ym9lX3BhbmVsKHBhbmVsKTsKPiA+ICsgICAgICAgaW50IHJldDsKPiA+ICsKPiA+ICsgICAgICAg
aWYgKGJvZS0+ZW5hYmxlZCkKPiA+ICsgICAgICAgICAgICAgICByZXR1cm4gMDsKPiA+ICsKPiA+
ICsgICAgICAgcmV0ID0gYmFja2xpZ2h0X2VuYWJsZShib2UtPmJhY2tsaWdodCk7Cj4gPiArICAg
ICAgIGlmIChyZXQpIHsKPiA+ICsgICAgICAgICAgICAgICBkZXZfZXJyKHBhbmVsLT5kZXYsICJG
YWlsZWQgdG8gZW5hYmxlIGJhY2tsaWdodCAlZFxuIiwKPiA+ICsgICAgICAgICAgICAgICAgICAg
ICAgIHJldCk7Cj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIHJldDsKPiA+ICsgICAgICAgfQo+
ID4gKwo+ID4gKyAgICAgICBib2UtPmVuYWJsZWQgPSB0cnVlOwo+ID4gKwo+ID4gKyAgICAgICBy
ZXR1cm4gMDsKPiA+ICt9Cj4gPiArCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCBkcm1fZGlzcGxh
eV9tb2RlIGJvZV9kZWZhdWx0X21vZGUgPSB7Cj4gPiArICAgICAgIC5jbG9jayA9IDE1OTQyNSwK
PiA+ICsgICAgICAgLmhkaXNwbGF5ID0gMTIwMCwKPiA+ICsgICAgICAgLmhzeW5jX3N0YXJ0ID0g
MTIwMCArIDEwMCwKPiA+ICsgICAgICAgLmhzeW5jX2VuZCA9IDEyMDAgKyAxMDAgKyA0MCwKPiA+
ICsgICAgICAgLmh0b3RhbCA9IDEyMDAgKyAxMDAgKyA0MCArIDI0LAo+ID4gKyAgICAgICAudmRp
c3BsYXkgPSAxOTIwLAo+ID4gKyAgICAgICAudnN5bmNfc3RhcnQgPSAxOTIwICsgMTAsCj4gPiAr
ICAgICAgIC52c3luY19lbmQgPSAxOTIwICsgMTAgKyAxNCwKPiA+ICsgICAgICAgLnZ0b3RhbCA9
IDE5MjAgKyAxMCArIDE0ICsgNCwKPiA+ICsgICAgICAgLnZyZWZyZXNoID0gNjAsCj4gPiArICAg
ICAgIC50eXBlID0gRFJNX01PREVfVFlQRV9EUklWRVIgfCBEUk1fTU9ERV9UWVBFX1BSRUZFUlJF
RCwKPiA+ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcGFuZWxfZGVzYyBib2Vf
dHYxMDF3dW1fbmw2X2Rlc2MgPSB7Cj4gPiArICAgICAgIC5tb2RlcyA9ICZib2VfZGVmYXVsdF9t
b2RlLAo+ID4gKyAgICAgICAuYnBjID0gOCwKPiA+ICsgICAgICAgLnNpemUgPSB7Cj4gPiArICAg
ICAgICAgICAgICAgLndpZHRoID0gMjE2LAo+ID4gKyAgICAgICAgICAgICAgIC5oZWlnaHQgPSAx
MzUsCgpUaGlzIGlzIHdyb25nLCBhcyB0aGlzIGlzIGEgcG9ydHJhaXQgcGFuZWwsIHNob3VsZCBi
ZTogd2lkdGg9MTM1LCBoZWlnaHQ9MjE2LgoKPiA+ICsgICAgICAgfSwKPiA+ICsgICAgICAgLmxh
bmVzID0gNCwKPiA+ICsgICAgICAgLmZvcm1hdCA9IE1JUElfRFNJX0ZNVF9SR0I4ODgsCj4gPiAr
ICAgICAgIC5tb2RlX2ZsYWdzID0gTUlQSV9EU0lfTU9ERV9WSURFTyB8IE1JUElfRFNJX01PREVf
VklERU9fU1lOQ19QVUxTRSB8Cj4gPiArICAgICAgICAgICAgICAgICAgICAgTUlQSV9EU0lfTU9E
RV9MUE0sCj4gPiArICAgICAgIC5pbml0X2NtZHMgPSBib2VfaW5pdF9jbWQsCj4gPiArfTsKPiA+
ICsKPiA+ICtzdGF0aWMgaW50IGJvZV9wYW5lbF9nZXRfbW9kZXMoc3RydWN0IGRybV9wYW5lbCAq
cGFuZWwpCj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3QgYm9lX3BhbmVsICpib2UgPSB0b19ib2Vf
cGFuZWwocGFuZWwpOwo+ID4gKyAgICAgICBjb25zdCBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAq
bSA9IGJvZS0+ZGVzYy0+bW9kZXM7Cj4gPiArICAgICAgIHN0cnVjdCBkcm1fZGlzcGxheV9tb2Rl
ICptb2RlOwo+ID4gKwo+ID4gKyAgICAgICBtb2RlID0gZHJtX21vZGVfZHVwbGljYXRlKHBhbmVs
LT5kcm0sIG0pOwo+ID4gKyAgICAgICBpZiAoIW1vZGUpIHsKPiA+ICsgICAgICAgICAgICAgICBk
ZXZfZXJyKHBhbmVsLT5kZXYsICJmYWlsZWQgdG8gYWRkIG1vZGUgJXV4JXVAJXVcbiIsCj4gPiAr
ICAgICAgICAgICAgICAgICAgICAgICBtLT5oZGlzcGxheSwgbS0+dmRpc3BsYXksIG0tPnZyZWZy
ZXNoKTsKPiA+ICsgICAgICAgICAgICAgICByZXR1cm4gLUVOT01FTTsKPiA+ICsgICAgICAgfQo+
ID4gKwo+ID4gKyAgICAgICBkcm1fbW9kZV9zZXRfbmFtZShtb2RlKTsKPiA+ICsKPgo+IFNhbSBz
dWdnZXN0ZWQgYWRkaW5nIHRoaXMgaGVyZToKPiBtb2RlLT50eXBlID0gRFJNX01PREVfVFlQRV9E
UklWRVIgfCBEUk1fTU9ERV9UWVBFX1BSRUZFUlJFRDsKClNjcmFwIHRoYXQsIEkgc2VlIHRoYXQg
eW91IGFkZGVkIGl0IGluIGJvZV9kZWZhdWx0X21vZGUuCgo+Cj4gPiArICAgICAgIGRybV9tb2Rl
X3Byb2JlZF9hZGQocGFuZWwtPmNvbm5lY3RvciwgbW9kZSk7Cj4gPiArCj4gPiArICAgICAgIHBh
bmVsLT5jb25uZWN0b3ItPmRpc3BsYXlfaW5mby53aWR0aF9tbSA9IGJvZS0+ZGVzYy0+c2l6ZS53
aWR0aDsKPiA+ICsgICAgICAgcGFuZWwtPmNvbm5lY3Rvci0+ZGlzcGxheV9pbmZvLmhlaWdodF9t
bSA9IGJvZS0+ZGVzYy0+c2l6ZS5oZWlnaHQ7Cj4gPiArICAgICAgIHBhbmVsLT5jb25uZWN0b3It
PmRpc3BsYXlfaW5mby5icGMgPSBib2UtPmRlc2MtPmJwYzsKPiA+ICsKPiA+ICsgICAgICAgcmV0
dXJuIDE7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgZHJtX3BhbmVsX2Z1
bmNzIGJvZV9wYW5lbF9mdW5jcyA9IHsKPiA+ICsgICAgICAgLmRpc2FibGUgPSBib2VfcGFuZWxf
ZGlzYWJsZSwKPiA+ICsgICAgICAgLnVucHJlcGFyZSA9IGJvZV9wYW5lbF91bnByZXBhcmUsCj4g
PiArICAgICAgIC5wcmVwYXJlID0gYm9lX3BhbmVsX3ByZXBhcmUsCj4gPiArICAgICAgIC5lbmFi
bGUgPSBib2VfcGFuZWxfZW5hYmxlLAo+ID4gKyAgICAgICAuZ2V0X21vZGVzID0gYm9lX3BhbmVs
X2dldF9tb2RlcywKPiA+ICt9Owo+ID4gKwo+ID4gK3N0YXRpYyBpbnQgYm9lX3BhbmVsX2FkZChz
dHJ1Y3QgYm9lX3BhbmVsICpib2UpCj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3QgZGV2aWNlICpk
ZXYgPSAmYm9lLT5kc2ktPmRldjsKPiA+ICsKPiA+ICsgICAgICAgYm9lLT5hdmRkID0gZGV2bV9y
ZWd1bGF0b3JfZ2V0KGRldiwgImF2ZGQiKTsKPiA+ICsgICAgICAgaWYgKElTX0VSUihib2UtPmF2
ZGQpKQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiBQVFJfRVJSKGJvZS0+YXZkZCk7Cj4gPiAr
Cj4gPiArICAgICAgIGJvZS0+YXZlZSA9IGRldm1fcmVndWxhdG9yX2dldChkZXYsICJhdmVlIik7
Cj4gPiArICAgICAgIGlmIChJU19FUlIoYm9lLT5hdmVlKSkKPiA+ICsgICAgICAgICAgICAgICBy
ZXR1cm4gUFRSX0VSUihib2UtPmF2ZWUpOwo+ID4gKwo+ID4gKyAgICAgICBib2UtPnBwMTgwMCA9
IGRldm1fcmVndWxhdG9yX2dldChkZXYsICJwcDE4MDAiKTsKPiA+ICsgICAgICAgaWYgKElTX0VS
Uihib2UtPnBwMTgwMCkpCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIFBUUl9FUlIoYm9lLT5w
cDE4MDApOwo+ID4gKwo+ID4gKyAgICAgICBib2UtPmVuYWJsZV9ncGlvID0gZGV2bV9ncGlvZF9n
ZXQoZGV2LCAiZW5hYmxlIiwgR1BJT0RfT1VUX0xPVyk7Cj4gPiArICAgICAgIGlmIChJU19FUlIo
Ym9lLT5lbmFibGVfZ3BpbykpIHsKPiA+ICsgICAgICAgICAgICAgICBkZXZfZXJyKGRldiwgImNh
bm5vdCBnZXQgcmVzZXQtZ3Bpb3MgJWxkXG4iLAo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAg
UFRSX0VSUihib2UtPmVuYWJsZV9ncGlvKSk7Cj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIFBU
Ul9FUlIoYm9lLT5lbmFibGVfZ3Bpbyk7Cj4gPiArICAgICAgIH0KPiA+ICsKPiA+ICsgICAgICAg
Z3Bpb2Rfc2V0X3ZhbHVlKGJvZS0+ZW5hYmxlX2dwaW8sIDApOwo+ID4gKwo+ID4gKyAgICAgICBi
b2UtPmJhY2tsaWdodCA9IGRldm1fb2ZfZmluZF9iYWNrbGlnaHQoZGV2KTsKPiA+ICsgICAgICAg
aWYgKElTX0VSUihib2UtPmJhY2tsaWdodCkpCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIFBU
Ul9FUlIoYm9lLT5iYWNrbGlnaHQpOwo+ID4gKwo+ID4gKyAgICAgICBkcm1fcGFuZWxfaW5pdCgm
Ym9lLT5iYXNlKTsKPiA+ICsgICAgICAgYm9lLT5iYXNlLmZ1bmNzID0gJmJvZV9wYW5lbF9mdW5j
czsKPiA+ICsgICAgICAgYm9lLT5iYXNlLmRldiA9ICZib2UtPmRzaS0+ZGV2Owo+ID4gKwo+ID4g
KyAgICAgICByZXR1cm4gZHJtX3BhbmVsX2FkZCgmYm9lLT5iYXNlKTsKPiA+ICt9Cj4gPiArCj4g
PiArc3RhdGljIGludCBib2VfcGFuZWxfcHJvYmUoc3RydWN0IG1pcGlfZHNpX2RldmljZSAqZHNp
KQo+ID4gK3sKPiA+ICsgICAgICAgc3RydWN0IGJvZV9wYW5lbCAqYm9lOwo+ID4gKyAgICAgICBp
bnQgcmV0Owo+ID4gKyAgICAgICBjb25zdCBzdHJ1Y3QgcGFuZWxfZGVzYyAqZGVzYzsKPiA+ICsK
PiA+ICsgICAgICAgYm9lID0gZGV2bV9remFsbG9jKCZkc2ktPmRldiwgc2l6ZW9mKCpib2UpLCBH
RlBfS0VSTkVMKTsKPiA+ICsgICAgICAgaWYgKCFib2UpCj4gPiArICAgICAgICAgICAgICAgcmV0
dXJuIC1FTk9NRU07Cj4gPiArCj4gPiArICAgICAgIGRlc2MgPSBvZl9kZXZpY2VfZ2V0X21hdGNo
X2RhdGEoJmRzaS0+ZGV2KTsKPiA+ICsgICAgICAgZHNpLT5sYW5lcyA9IGRlc2MtPmxhbmVzOwo+
ID4gKyAgICAgICBkc2ktPmZvcm1hdCA9IGRlc2MtPmZvcm1hdDsKPiA+ICsgICAgICAgZHNpLT5t
b2RlX2ZsYWdzID0gZGVzYy0+bW9kZV9mbGFnczsKPiA+ICsgICAgICAgYm9lLT5kZXNjID0gZGVz
YzsKPiA+ICsgICAgICAgYm9lLT5kc2kgPSBkc2k7Cj4gPiArICAgICAgIHJldCA9IGJvZV9wYW5l
bF9hZGQoYm9lKTsKPiA+ICsgICAgICAgaWYgKHJldCA8IDApCj4gPiArICAgICAgICAgICAgICAg
cmV0dXJuIHJldDsKPiA+ICsKPiA+ICsgICAgICAgbWlwaV9kc2lfc2V0X2RydmRhdGEoZHNpLCBi
b2UpOwo+ID4gKwo+ID4gKyAgICAgICByZXR1cm4gbWlwaV9kc2lfYXR0YWNoKGRzaSk7Cj4gPiAr
fQo+ID4gKwo+ID4gK3N0YXRpYyBpbnQgYm9lX3BhbmVsX3JlbW92ZShzdHJ1Y3QgbWlwaV9kc2lf
ZGV2aWNlICpkc2kpCj4gPiArewo+ID4gKyAgICAgICBzdHJ1Y3QgYm9lX3BhbmVsICpib2UgPSBt
aXBpX2RzaV9nZXRfZHJ2ZGF0YShkc2kpOwo+ID4gKyAgICAgICBpbnQgcmV0Owo+ID4gKwo+ID4g
KyAgICAgICByZXQgPSBib2VfcGFuZWxfZGlzYWJsZSgmYm9lLT5iYXNlKTsKPiA+ICsgICAgICAg
aWYgKHJldCA8IDApCj4gPiArICAgICAgICAgICAgICAgZGV2X2VycigmZHNpLT5kZXYsICJmYWls
ZWQgdG8gZGlzYWJsZSBwYW5lbDogJWRcbiIsIHJldCk7Cj4gPiArCj4gPiArICAgICAgIHJldCA9
IG1pcGlfZHNpX2RldGFjaChkc2kpOwo+ID4gKyAgICAgICBpZiAocmV0IDwgMCkKPiA+ICsgICAg
ICAgICAgICAgICBkZXZfZXJyKCZkc2ktPmRldiwgImZhaWxlZCB0byBkZXRhY2ggZnJvbSBEU0kg
aG9zdDogJWRcbiIsIHJldCk7Cj4gPiArCj4gPiArICAgICAgIGlmIChib2UtPmJhc2UuZGV2KQo+
ID4gKyAgICAgICAgICAgICAgIGRybV9wYW5lbF9yZW1vdmUoJmJvZS0+YmFzZSk7Cj4gPiArCj4g
PiArICAgICAgIHJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgdm9pZCBib2VfcGFu
ZWxfc2h1dGRvd24oc3RydWN0IG1pcGlfZHNpX2RldmljZSAqZHNpKQo+ID4gK3sKPiA+ICsgICAg
ICAgc3RydWN0IGJvZV9wYW5lbCAqYm9lID0gbWlwaV9kc2lfZ2V0X2RydmRhdGEoZHNpKTsKPiA+
ICsKPiA+ICsgICAgICAgYm9lX3BhbmVsX2Rpc2FibGUoJmJvZS0+YmFzZSk7Cj4gPiArfQo+ID4g
Kwo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIGJvZV9vZl9tYXRjaFtdID0g
ewo+ID4gKyAgICAgICB7IC5jb21wYXRpYmxlID0gImJvZSx0djEwMXd1bS1ubDYiLAo+ID4gKyAg
ICAgICAgIC5kYXRhID0gJmJvZV90djEwMXd1bV9ubDZfZGVzYwo+ID4gKyAgICAgICB9LAo+ID4g
KyAgICAgICB7IC8qIHNlbnRpbmVsICovIH0KPiA+ICt9Owo+ID4gK01PRFVMRV9ERVZJQ0VfVEFC
TEUob2YsIGJvZV9vZl9tYXRjaCk7Cj4gPiArCj4gPiArc3RhdGljIHN0cnVjdCBtaXBpX2RzaV9k
cml2ZXIgYm9lX3BhbmVsX2RyaXZlciA9IHsKPiA+ICsgICAgICAgLmRyaXZlciA9IHsKPiA+ICsg
ICAgICAgICAgICAgICAubmFtZSA9ICJwYW5lbC1ib2UtdHYxMDF3dW0tbmw2IiwKPiA+ICsgICAg
ICAgICAgICAgICAub2ZfbWF0Y2hfdGFibGUgPSBib2Vfb2ZfbWF0Y2gsCj4gPiArICAgICAgIH0s
Cj4gPiArICAgICAgIC5wcm9iZSA9IGJvZV9wYW5lbF9wcm9iZSwKPiA+ICsgICAgICAgLnJlbW92
ZSA9IGJvZV9wYW5lbF9yZW1vdmUsCj4gPiArICAgICAgIC5zaHV0ZG93biA9IGJvZV9wYW5lbF9z
aHV0ZG93biwKPiA+ICt9Owo+ID4gK21vZHVsZV9taXBpX2RzaV9kcml2ZXIoYm9lX3BhbmVsX2Ry
aXZlcik7Cj4gPiArCj4gPiArTU9EVUxFX0FVVEhPUigiSml0YW8gU2hpIDxqaXRhby5zaGlAbWVk
aWF0ZWsuY29tPiIpOwo+ID4gK01PRFVMRV9ERVNDUklQVElPTigiQk9FIHR2MTAxd3VtLW5sNiAx
MjAweDE5MjAgdmlkZW8gbW9kZSBwYW5lbCBkcml2ZXIiKTsKPiA+ICtNT0RVTEVfTElDRU5TRSgi
R1BMIHYyIik7Cj4gPiAtLQo+ID4gMi4yMS4wCj4gPgo+ID4gX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX18KPiA+IGRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKPiA+
IGRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiA+IGh0dHBzOi8vbGlzdHMuZnJlZWRl
c2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCl9fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRl
dmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9t
YWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbA==

From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <SRS0=hmmp=UY=lists.infradead.org=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@kernel.org>
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
	aws-us-west-2-korg-lkml-1.web.codeaurora.org
X-Spam-Level: 
X-Spam-Status: No, score=-4.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,
	DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,
	SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED
	autolearn=unavailable autolearn_force=no version=3.4.0
Received: from mail.kernel.org (mail.kernel.org [198.145.29.99])
	by smtp.lore.kernel.org (Postfix) with ESMTP id 0E626C4646B
	for <infradead-linux-arm-kernel@archiver.kernel.org>; Tue, 25 Jun 2019 00:42:40 +0000 (UTC)
Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133])
	(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
	(No client certificate requested)
	by mail.kernel.org (Postfix) with ESMTPS id A37B6205C9
	for <infradead-linux-arm-kernel@archiver.kernel.org>; Tue, 25 Jun 2019 00:42:39 +0000 (UTC)
Authentication-Results: mail.kernel.org;
	dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="DHH/AlaL";
	dkim=fail reason="signature verification failed" (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="a78p5hkW"
DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A37B6205C9
Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org
Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
	d=lists.infradead.org; s=bombadil.20170209; h=Sender:
	Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:
	List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:
	In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description:
	Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:
	List-Owner; bh=BikGEItaY8+Md9ea+8L364xYH+6mRhrmoP6uao2T7cQ=; b=DHH/AlaLzTgBlH
	SsbWP7EAbNWO1X55nref8PGVurPDgZbTKm99rGki3AeYnyw+HumZNZkQLP4u87DZ4/SM2M7zCBrhH
	ooEoubuGh03T2+av72xnPZ0YdjjzFpq8mAQyj8C+1uJWShmorR4WL74ujmnQMaPfHJPxlw0+UkDNb
	y7rsFk53bO3uJal/yoOkl6lzZmZ9+Tv54DajyTVUf5V1I/+mLPmGikC8s35kLRCdaTfjzTxVQoosd
	WcCSRO9L4OM4F7UMWKr0WmBRNn13Hxsy1a2+i/UbHOeEhQcxuPWxpA5oFCRlNzXrBiC/LxRDyw7MN
	2qOs8UBPdIbwSDlxO0ng==;
Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org)
	by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux))
	id 1hfZXf-0008TY-7y; Tue, 25 Jun 2019 00:42:35 +0000
Received: from mail-qt1-x841.google.com ([2607:f8b0:4864:20::841])
 by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux))
 id 1hfZXZ-0008Ri-Iq
 for linux-arm-kernel@lists.infradead.org; Tue, 25 Jun 2019 00:42:32 +0000
Received: by mail-qt1-x841.google.com with SMTP id p15so16591179qtl.3
 for <linux-arm-kernel@lists.infradead.org>;
 Mon, 24 Jun 2019 17:42:29 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google;
 h=mime-version:references:in-reply-to:from:date:message-id:subject:to
 :cc; bh=D0CatzhMtPEqvzuGSZZ/Q3MqqvQzjh5y8rhA8hbW6wI=;
 b=a78p5hkWEU9pITE2WlOzVrvy1+Bd3DoHqUYTxcohn3/jicZ4BT1bVNTF0ZkH4EanZM
 /MGTT4aGn774EQzPilUErLwm6/larBYmP9L67V7pGknpqwcoDRvSoK+UimzH/9Cwkz5n
 JDQoSlMatN3leySyGnMtW2vgdGcu/a25fH8OA=
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
 d=1e100.net; s=20161025;
 h=x-gm-message-state:mime-version:references:in-reply-to:from:date
 :message-id:subject:to:cc;
 bh=D0CatzhMtPEqvzuGSZZ/Q3MqqvQzjh5y8rhA8hbW6wI=;
 b=tOsWj118iOZT9C8Io+Rpj0rnH9HwPe/3OMgLkRYg6/k98crB9qNAHpcZgIndlZ/rrb
 cgOiohHuE/aXRV2dhq4e+HcwlvdNG+hj8bgPxSuRVAguBlvcRV3Z6ysruWbO6aUQ7p4J
 I4ljIOYXNkqYTGaQkbZtcIWnY6uKupgj8TuuYSuxxvCCtSALAUZUZWUVLKgCqX5yRjUo
 9kNaWebX5LWJ4nKFT2AJ+eRbMxYgAW1s06wS1Qao41llMr+urosIZpJBD2qkMqahPOxl
 43n1bWkPoM3PJhGbd6p99nDjB/KXN5rB3X2PaPlt4nw8TqRJ5o9mOf0B+nKqv5gFTK6y
 bupA==
X-Gm-Message-State: APjAAAVYt57yaroMVGrAwBqA7eYYNaaXfD3A0YVwsPsLSRFjGhF/ng45
 yOXbXfU1TvS6bnPcfcQfSDQRffG3idxvNHFdy92C1w==
X-Google-Smtp-Source: APXvYqz89tH5leyNwSwZvrzbPI8hzk5ZFa+L9cXsOqWm3c0MO/uRmaRHdIt4onolh51eRNIVIZpsb78QxJME3gZZLNY=
X-Received: by 2002:a0c:b04d:: with SMTP id l13mr61365864qvc.104.1561423348081; 
 Mon, 24 Jun 2019 17:42:28 -0700 (PDT)
MIME-Version: 1.0
References: <20190624060343.62451-1-jitao.shi@mediatek.com>
 <20190624060343.62451-3-jitao.shi@mediatek.com>
 <CANMq1KABzuKu1nyP4Mq-6eHPA3tFZ+AViAaouzrgHu9RL4i-6A@mail.gmail.com>
In-Reply-To: <CANMq1KABzuKu1nyP4Mq-6eHPA3tFZ+AViAaouzrgHu9RL4i-6A@mail.gmail.com>
From: Nicolas Boichat <drinkcat@chromium.org>
Date: Tue, 25 Jun 2019 08:42:16 +0800
Message-ID: <CANMq1KBS0DhVcM=EMqNQfMuh91WJ-Vk5EZvVKkLQQq2VECjraA@mail.gmail.com>
Subject: Re: [v2 2/2] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video
 mode panel
To: Jitao Shi <jitao.shi@mediatek.com>
X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 
X-CRM114-CacheID: sfid-20190624_174229_663272_B0C729E9 
X-CRM114-Status: GOOD (  19.50  )
X-BeenThere: linux-arm-kernel@lists.infradead.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: <linux-arm-kernel.lists.infradead.org>
List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-arm-kernel>, 
 <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>
List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
List-Post: <mailto:linux-arm-kernel@lists.infradead.org>
List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>
List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, 
 <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>
Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org,
 David Airlie <airlied@linux.ie>, stonea168@163.com,
 dri-devel@lists.freedesktop.org, Ajay Kumar <ajaykumar.rs@samsung.com>,
 Vincent Palatin <vpalatin@chromium.org>, cawa cheng <cawa.cheng@mediatek.com>,
 Yingjoe Chen <yingjoe.chen@mediatek.com>, Thierry Reding <treding@nvidia.com>,
 Sean Paul <seanpaul@chromium.org>, linux-pwm@vger.kernel.org,
 Pawel Moll <pawel.moll@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>,
 Rob Herring <robh+dt@kernel.org>,
 "moderated list:ARM/Mediatek SoC support" <linux-mediatek@lists.infradead.org>,
 Russell King <rmk+kernel@arm.linux.org.uk>,
 Matthias Brugger <matthias.bgg@gmail.com>,
 Eddie Huang <eddie.huang@mediatek.com>,
 linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
 Rahul Sharma <rahul.sharma@samsung.com>,
 srv_heupstream <srv_heupstream@mediatek.com>,
 lkml <linux-kernel@vger.kernel.org>, Sascha Hauer <kernel@pengutronix.de>,
 Andy Yan <andy.yan@rock-chips.com>
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org

On Mon, Jun 24, 2019 at 4:25 PM Nicolas Boichat <drinkcat@chromium.org> wrote:
>
> On Mon, Jun 24, 2019 at 2:04 PM Jitao Shi <jitao.shi@mediatek.com> wrote:
> >
> > Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.
> >
> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> > ---
> >  drivers/gpu/drm/panel/Kconfig                 |  10 +
> >  drivers/gpu/drm/panel/Makefile                |   1 +
> >  .../gpu/drm/panel/panel-boe-tv101wum-nl6.c    | 715 ++++++++++++++++++
> >  3 files changed, 726 insertions(+)
> >  create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> >
> > diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> > index e36dbb4df867..2b055ce0700b 100644
> > --- a/drivers/gpu/drm/panel/Kconfig
> > +++ b/drivers/gpu/drm/panel/Kconfig
> > @@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
> >           reference designs. The panel is detected using special registers
> >           in the Versatile family syscon registers.
> >
> > +config DRM_PANEL_BOE_TV101WUM_NL6
> > +       tristate "BOE TV101WUM 1200x1920 panel"
> > +       depends on OF
> > +       depends on DRM_MIPI_DSI
> > +       depends on BACKLIGHT_CLASS_DEVICE
> > +       help
> > +         Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
> > +         DSI Video Mode panel
> > +
> >  config DRM_PANEL_LVDS
> >         tristate "Generic LVDS panel driver"
> >         depends on OF
> > @@ -272,4 +281,5 @@ config DRM_PANEL_TRULY_NT35597_WQXGA
> >         help
> >           Say Y here if you want to enable support for Truly NT35597 WQXGA Dual DSI
> >           Video Mode panel
> > +
>
> Drop this change.
>
> >  endmenu
> > diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> > index 78e3dc376bdd..8d009223c44e 100644
> > --- a/drivers/gpu/drm/panel/Makefile
> > +++ b/drivers/gpu/drm/panel/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
> > +obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
> >  obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
> >  obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
> >  obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
> > diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > new file mode 100644
> > index 000000000000..6e06c8506623
> > --- /dev/null
> > +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> > @@ -0,0 +1,715 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Jitao Shi <jitao.shi@mediatek.com>
> > + */
> > +
> > +#include <linux/backlight.h>
> > +#include <linux/delay.h>
> > +#include <linux/gpio/consumer.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/regulator/consumer.h>
> > +
> > +#include <drm/drm_crtc.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +#include <drm/drm_panel.h>
> > +
> > +#include <video/mipi_display.h>
> > +
> > +struct panel_desc {
> > +       const struct drm_display_mode *modes;
> > +       unsigned int bpc;
> > +
> > +       /**
> > +        * @width: width (in millimeters) of the panel's active display area
> > +        * @height: height (in millimeters) of the panel's active display area
> > +        */
> > +       struct {
> > +               unsigned int width;
> > +               unsigned int height;
> > +       } size;
> > +
> > +       unsigned long mode_flags;
> > +       enum mipi_dsi_pixel_format format;
> > +       const struct panel_init_cmd *init_cmds;
> > +       unsigned int lanes;
> > +};
> > +
> > +struct boe_panel {
> > +       struct drm_panel base;
> > +       struct mipi_dsi_device *dsi;
> > +
> > +       const struct panel_desc *desc;
> > +
> > +       struct backlight_device *backlight;
> > +       struct regulator *pp1800;
> > +       struct regulator *avee;
> > +       struct regulator *avdd;
> > +       struct gpio_desc *enable_gpio;
> > +
> > +       bool prepared;
> > +       bool enabled;
> > +
> > +       const struct drm_display_mode *mode;
> > +};
> > +
> > +enum dsi_cmd_type {
> > +       INIT_DCS_CMD,
> > +       DELAY_CMD,
> > +};
> > +
> > +struct panel_init_cmd {
> > +       enum dsi_cmd_type type;
> > +       size_t len;
> > +       const char *data;
> > +};
> > +
> > +#define _INIT_DCS_CMD(...) { \
> > +       .type = INIT_DCS_CMD, \
> > +       .len = sizeof((char[]){__VA_ARGS__}), \
> > +       .data = (char[]){__VA_ARGS__} }
> > +
> > +#define _INIT_DELAY_CMD(...) { \
> > +       .type = DELAY_CMD,\
> > +       .len = sizeof((char[]){__VA_ARGS__}), \
> > +       .data = (char[]){__VA_ARGS__} }
> > +
> > +static const struct panel_init_cmd boe_init_cmd[] = {
> > +       _INIT_DELAY_CMD(24),
> > +       _INIT_DCS_CMD(0xB0, 0x05),
> > +       _INIT_DCS_CMD(0xB1, 0xE5),
> > +       _INIT_DCS_CMD(0xB3, 0x52),
> > +       _INIT_DCS_CMD(0xB0, 0x00),
> > +       _INIT_DCS_CMD(0xB3, 0x88),
> > +       _INIT_DCS_CMD(0xB0, 0x04),
> > +       _INIT_DCS_CMD(0xB8, 0x00),
> > +       _INIT_DCS_CMD(0xB0, 0x00),
> > +       _INIT_DCS_CMD(0xB6, 0x03),
> > +       _INIT_DCS_CMD(0xBA, 0x8B),
> > +       _INIT_DCS_CMD(0xBF, 0x1A),
> > +       _INIT_DCS_CMD(0xC0, 0x0F),
> > +       _INIT_DCS_CMD(0xC2, 0x0C),
> > +       _INIT_DCS_CMD(0xC3, 0x02),
> > +       _INIT_DCS_CMD(0xC4, 0x0C),
> > +       _INIT_DCS_CMD(0xC5, 0x02),
> > +       _INIT_DCS_CMD(0xB0, 0x01),
> > +       _INIT_DCS_CMD(0xE0, 0x26),
> > +       _INIT_DCS_CMD(0xE1, 0x26),
> > +       _INIT_DCS_CMD(0xDC, 0x00),
> > +       _INIT_DCS_CMD(0xDD, 0x00),
> > +       _INIT_DCS_CMD(0xCC, 0x26),
> > +       _INIT_DCS_CMD(0xCD, 0x26),
> > +       _INIT_DCS_CMD(0xC8, 0x00),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xD2, 0x03),
> > +       _INIT_DCS_CMD(0xD3, 0x03),
> > +       _INIT_DCS_CMD(0xE6, 0x04),
> > +       _INIT_DCS_CMD(0xE7, 0x04),
> > +       _INIT_DCS_CMD(0xC4, 0x09),
> > +       _INIT_DCS_CMD(0xC5, 0x09),
> > +       _INIT_DCS_CMD(0xD8, 0x0A),
> > +       _INIT_DCS_CMD(0xD9, 0x0A),
> > +       _INIT_DCS_CMD(0xC2, 0x0B),
> > +       _INIT_DCS_CMD(0xC3, 0x0B),
> > +       _INIT_DCS_CMD(0xD6, 0x0C),
> > +       _INIT_DCS_CMD(0xD7, 0x0C),
> > +       _INIT_DCS_CMD(0xC0, 0x05),
> > +       _INIT_DCS_CMD(0xC1, 0x05),
> > +       _INIT_DCS_CMD(0xD4, 0x06),
> > +       _INIT_DCS_CMD(0xD5, 0x06),
> > +       _INIT_DCS_CMD(0xCA, 0x07),
> > +       _INIT_DCS_CMD(0xCB, 0x07),
> > +       _INIT_DCS_CMD(0xDE, 0x08),
> > +       _INIT_DCS_CMD(0xDF, 0x08),
> > +       _INIT_DCS_CMD(0xB0, 0x02),
> > +       _INIT_DCS_CMD(0xC0, 0x00),
> > +       _INIT_DCS_CMD(0xC1, 0x0D),
> > +       _INIT_DCS_CMD(0xC2, 0x17),
> > +       _INIT_DCS_CMD(0xC3, 0x26),
> > +       _INIT_DCS_CMD(0xC4, 0x31),
> > +       _INIT_DCS_CMD(0xC5, 0x1C),
> > +       _INIT_DCS_CMD(0xC6, 0x2C),
> > +       _INIT_DCS_CMD(0xC7, 0x33),
> > +       _INIT_DCS_CMD(0xC8, 0x31),
> > +       _INIT_DCS_CMD(0xC9, 0x37),
> > +       _INIT_DCS_CMD(0xCA, 0x37),
> > +       _INIT_DCS_CMD(0xCB, 0x37),
> > +       _INIT_DCS_CMD(0xCC, 0x39),
> > +       _INIT_DCS_CMD(0xCD, 0x2E),
> > +       _INIT_DCS_CMD(0xCE, 0x2F),
> > +       _INIT_DCS_CMD(0xCF, 0x2F),
> > +       _INIT_DCS_CMD(0xD0, 0x07),
> > +       _INIT_DCS_CMD(0xD2, 0x00),
> > +       _INIT_DCS_CMD(0xD3, 0x0D),
> > +       _INIT_DCS_CMD(0xD4, 0x17),
> > +       _INIT_DCS_CMD(0xD5, 0x26),
> > +       _INIT_DCS_CMD(0xD6, 0x31),
> > +       _INIT_DCS_CMD(0xD7, 0x3F),
> > +       _INIT_DCS_CMD(0xD8, 0x3F),
> > +       _INIT_DCS_CMD(0xD9, 0x3F),
> > +       _INIT_DCS_CMD(0xDA, 0x3F),
> > +       _INIT_DCS_CMD(0xDB, 0x37),
> > +       _INIT_DCS_CMD(0xDC, 0x37),
> > +       _INIT_DCS_CMD(0xDD, 0x37),
> > +       _INIT_DCS_CMD(0xDE, 0x39),
> > +       _INIT_DCS_CMD(0xDF, 0x2E),
> > +       _INIT_DCS_CMD(0xE0, 0x2F),
> > +       _INIT_DCS_CMD(0xE1, 0x2F),
> > +       _INIT_DCS_CMD(0xE2, 0x07),
> > +       _INIT_DCS_CMD(0xB0, 0x03),
> > +       _INIT_DCS_CMD(0xC8, 0x0B),
> > +       _INIT_DCS_CMD(0xC9, 0x07),
> > +       _INIT_DCS_CMD(0xC3, 0x00),
> > +       _INIT_DCS_CMD(0xE7, 0x00),
> > +       _INIT_DCS_CMD(0xC5, 0x2A),
> > +       _INIT_DCS_CMD(0xDE, 0x2A),
> > +       _INIT_DCS_CMD(0xCA, 0x43),
> > +       _INIT_DCS_CMD(0xC9, 0x07),
> > +       _INIT_DCS_CMD(0xE4, 0xC0),
> > +       _INIT_DCS_CMD(0xE5, 0x0D),
> > +       _INIT_DCS_CMD(0xCB, 0x00),
> > +       _INIT_DCS_CMD(0xB0, 0x06),
> > +       _INIT_DCS_CMD(0xB8, 0xA5),
> > +       _INIT_DCS_CMD(0xC0, 0xA5),
> > +       _INIT_DCS_CMD(0xC7, 0x0F),
> > +       _INIT_DCS_CMD(0xD5, 0x32),
> > +       _INIT_DCS_CMD(0xB8, 0x00),
> > +       _INIT_DCS_CMD(0xC0, 0x00),
> > +       _INIT_DCS_CMD(0xBC, 0x00),
> > +       _INIT_DCS_CMD(0xB0, 0x07),
> > +       _INIT_DCS_CMD(0xB1, 0x00),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x0F),
> > +       _INIT_DCS_CMD(0xB4, 0x25),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4E),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x97),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x22),
> > +       _INIT_DCS_CMD(0xBB, 0xA4),
> > +       _INIT_DCS_CMD(0xBC, 0x2B),
> > +       _INIT_DCS_CMD(0xBD, 0x2F),
> > +       _INIT_DCS_CMD(0xBE, 0xA9),
> > +       _INIT_DCS_CMD(0xBF, 0x25),
> > +       _INIT_DCS_CMD(0xC0, 0x61),
> > +       _INIT_DCS_CMD(0xC1, 0x97),
> > +       _INIT_DCS_CMD(0xC2, 0xB2),
> > +       _INIT_DCS_CMD(0xC3, 0xCD),
> > +       _INIT_DCS_CMD(0xC4, 0xD9),
> > +       _INIT_DCS_CMD(0xC5, 0xE7),
> > +       _INIT_DCS_CMD(0xC6, 0xF4),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x08),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x05),
> > +       _INIT_DCS_CMD(0xB3, 0x11),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x98),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x23),
> > +       _INIT_DCS_CMD(0xBB, 0xA6),
> > +       _INIT_DCS_CMD(0xBC, 0x2C),
> > +       _INIT_DCS_CMD(0xBD, 0x30),
> > +       _INIT_DCS_CMD(0xBE, 0xAA),
> > +       _INIT_DCS_CMD(0xBF, 0x26),
> > +       _INIT_DCS_CMD(0xC0, 0x62),
> > +       _INIT_DCS_CMD(0xC1, 0x9B),
> > +       _INIT_DCS_CMD(0xC2, 0xB5),
> > +       _INIT_DCS_CMD(0xC3, 0xCF),
> > +       _INIT_DCS_CMD(0xC4, 0xDB),
> > +       _INIT_DCS_CMD(0xC5, 0xE8),
> > +       _INIT_DCS_CMD(0xC6, 0xF5),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x09),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x16),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x3B),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x73),
> > +       _INIT_DCS_CMD(0xB8, 0x99),
> > +       _INIT_DCS_CMD(0xB9, 0xE0),
> > +       _INIT_DCS_CMD(0xBA, 0x26),
> > +       _INIT_DCS_CMD(0xBB, 0xAD),
> > +       _INIT_DCS_CMD(0xBC, 0x36),
> > +       _INIT_DCS_CMD(0xBD, 0x3A),
> > +       _INIT_DCS_CMD(0xBE, 0xAE),
> > +       _INIT_DCS_CMD(0xBF, 0x2A),
> > +       _INIT_DCS_CMD(0xC0, 0x66),
> > +       _INIT_DCS_CMD(0xC1, 0x9E),
> > +       _INIT_DCS_CMD(0xC2, 0xB8),
> > +       _INIT_DCS_CMD(0xC3, 0xD1),
> > +       _INIT_DCS_CMD(0xC4, 0xDD),
> > +       _INIT_DCS_CMD(0xC5, 0xE9),
> > +       _INIT_DCS_CMD(0xC6, 0xF6),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x0A),
> > +       _INIT_DCS_CMD(0xB1, 0x00),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x0F),
> > +       _INIT_DCS_CMD(0xB4, 0x25),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4E),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x97),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x22),
> > +       _INIT_DCS_CMD(0xBB, 0xA4),
> > +       _INIT_DCS_CMD(0xBC, 0x2B),
> > +       _INIT_DCS_CMD(0xBD, 0x2F),
> > +       _INIT_DCS_CMD(0xBE, 0xA9),
> > +       _INIT_DCS_CMD(0xBF, 0x25),
> > +       _INIT_DCS_CMD(0xC0, 0x61),
> > +       _INIT_DCS_CMD(0xC1, 0x97),
> > +       _INIT_DCS_CMD(0xC2, 0xB2),
> > +       _INIT_DCS_CMD(0xC3, 0xCD),
> > +       _INIT_DCS_CMD(0xC4, 0xD9),
> > +       _INIT_DCS_CMD(0xC5, 0xE7),
> > +       _INIT_DCS_CMD(0xC6, 0xF4),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x0B),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x05),
> > +       _INIT_DCS_CMD(0xB3, 0x11),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x39),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x72),
> > +       _INIT_DCS_CMD(0xB8, 0x98),
> > +       _INIT_DCS_CMD(0xB9, 0xDC),
> > +       _INIT_DCS_CMD(0xBA, 0x23),
> > +       _INIT_DCS_CMD(0xBB, 0xA6),
> > +       _INIT_DCS_CMD(0xBC, 0x2C),
> > +       _INIT_DCS_CMD(0xBD, 0x30),
> > +       _INIT_DCS_CMD(0xBE, 0xAA),
> > +       _INIT_DCS_CMD(0xBF, 0x26),
> > +       _INIT_DCS_CMD(0xC0, 0x62),
> > +       _INIT_DCS_CMD(0xC1, 0x9B),
> > +       _INIT_DCS_CMD(0xC2, 0xB5),
> > +       _INIT_DCS_CMD(0xC3, 0xCF),
> > +       _INIT_DCS_CMD(0xC4, 0xDB),
> > +       _INIT_DCS_CMD(0xC5, 0xE8),
> > +       _INIT_DCS_CMD(0xC6, 0xF5),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x0C),
> > +       _INIT_DCS_CMD(0xB1, 0x04),
> > +       _INIT_DCS_CMD(0xB2, 0x02),
> > +       _INIT_DCS_CMD(0xB3, 0x16),
> > +       _INIT_DCS_CMD(0xB4, 0x24),
> > +       _INIT_DCS_CMD(0xB5, 0x3B),
> > +       _INIT_DCS_CMD(0xB6, 0x4F),
> > +       _INIT_DCS_CMD(0xB7, 0x73),
> > +       _INIT_DCS_CMD(0xB8, 0x99),
> > +       _INIT_DCS_CMD(0xB9, 0xE0),
> > +       _INIT_DCS_CMD(0xBA, 0x26),
> > +       _INIT_DCS_CMD(0xBB, 0xAD),
> > +       _INIT_DCS_CMD(0xBC, 0x36),
> > +       _INIT_DCS_CMD(0xBD, 0x3A),
> > +       _INIT_DCS_CMD(0xBE, 0xAE),
> > +       _INIT_DCS_CMD(0xBF, 0x2A),
> > +       _INIT_DCS_CMD(0xC0, 0x66),
> > +       _INIT_DCS_CMD(0xC1, 0x9E),
> > +       _INIT_DCS_CMD(0xC2, 0xB8),
> > +       _INIT_DCS_CMD(0xC3, 0xD1),
> > +       _INIT_DCS_CMD(0xC4, 0xDD),
> > +       _INIT_DCS_CMD(0xC5, 0xE9),
> > +       _INIT_DCS_CMD(0xC6, 0xF6),
> > +       _INIT_DCS_CMD(0xC7, 0xFA),
> > +       _INIT_DCS_CMD(0xC8, 0xFC),
> > +       _INIT_DCS_CMD(0xC9, 0x00),
> > +       _INIT_DCS_CMD(0xCA, 0x00),
> > +       _INIT_DCS_CMD(0xCB, 0x16),
> > +       _INIT_DCS_CMD(0xCC, 0xAF),
> > +       _INIT_DCS_CMD(0xCD, 0xFF),
> > +       _INIT_DCS_CMD(0xCE, 0xFF),
> > +       _INIT_DCS_CMD(0xB0, 0x00),
> > +       _INIT_DCS_CMD(0xB3, 0x08),
> > +       _INIT_DCS_CMD(0xB0, 0x04),
> > +       _INIT_DCS_CMD(0xB8, 0x68),
> > +       _INIT_DELAY_CMD(150),
> > +       {},
> > +};
> > +
> > +static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
> > +{
> > +       return container_of(panel, struct boe_panel, base);
> > +}
> > +
> > +static int boe_panel_init(struct boe_panel *boe)
> > +{
> > +       struct mipi_dsi_device *dsi = boe->dsi;
> > +       struct drm_panel *panel = &boe->base;
> > +       int err, i;
> > +
> > +       if (boe->desc->init_cmds) {
> > +               const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
> > +
> > +               for (i = 0; init_cmds[i].len != 0; i++) {
> > +                       const struct panel_init_cmd *cmd = &init_cmds[i];
> > +
> > +                       switch (cmd->type) {
> > +                       case DELAY_CMD:
> > +                               msleep(cmd->data[0]);
> > +                               err = 0;
> > +                               break;
> > +
> > +                       case INIT_DCS_CMD:
> > +                               err = mipi_dsi_dcs_write(dsi, cmd->data[0],
> > +                                                        cmd->len <= 1 ? NULL :
> > +                                                        &cmd->data[1],
> > +                                                        cmd->len - 1);
> > +                               break;
> > +                       }
> > +
> > +                       if (err < 0) {
> > +                               dev_err(panel->dev,
> > +                                       "failed to write command %u\n", i);
> > +                               return err;
> > +                       }
> > +               }
> > +       }
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_off(struct boe_panel *boe)
> > +{
> > +       struct mipi_dsi_device *dsi = boe->dsi;
> > +       int ret;
> > +
> > +       dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
> > +
> > +       ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_disable(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +
> > +       if (!boe->enabled)
> > +               return 0;
> > +
> > +       backlight_disable(boe->backlight);
> > +
> > +       boe->enabled = false;
> > +
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_unprepare(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       int ret;
> > +
> > +       if (!boe->prepared)
> > +               return 0;
> > +
> > +       ret = boe_panel_off(boe);
> > +       if (ret < 0) {
> > +               dev_err(panel->dev, "failed to set panel off: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       msleep(150);
> > +       if (boe->enable_gpio)
> > +               gpiod_set_value(boe->enable_gpio, 0);
> > +       usleep_range(500, 1000);
> > +       regulator_disable(boe->avee);
> > +       regulator_disable(boe->avdd);
> > +       usleep_range(5000, 7000);
> > +       regulator_disable(boe->pp1800);
> > +
> > +       boe->prepared = false;
> > +
> > +       return 0;
> > +}
> > +
> > +static int boe_panel_prepare(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       int ret;
> > +
> > +       if (boe->prepared)
> > +               return 0;
> > +
> > +       if (boe->enable_gpio) {
> > +               gpiod_set_value(boe->enable_gpio, 0);
> > +               usleep_range(1000, 1500);
> > +       }
> > +
> > +       ret = regulator_enable(boe->pp1800);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       usleep_range(3000, 5000);
> > +
> > +       ret = regulator_enable(boe->avdd);
> > +       if (ret < 0)
> > +               goto poweroff1v8;
> > +       ret = regulator_enable(boe->avee);
> > +       if (ret < 0)
> > +               goto poweroffavdd;
> > +
> > +       msleep(100);
> > +
> > +       if (boe->enable_gpio) {
> > +               gpiod_set_value(boe->enable_gpio, 1);
> > +               usleep_range(10000, 12000);
> > +       }
> > +
> > +       ret = boe_panel_init(boe);
> > +       if (ret < 0) {
> > +               dev_err(panel->dev, "failed to init panel: %d\n", ret);
> > +               goto poweroff;
> > +       }
> > +
> > +       boe->prepared = true;
> > +
> > +       return 0;
> > +
> > +poweroff:
> > +       regulator_disable(boe->avee);
> > +poweroffavdd:
> > +       regulator_disable(boe->avdd);
> > +poweroff1v8:
> > +       usleep_range(5000, 7000);
> > +       regulator_disable(boe->pp1800);
> > +       if (boe->enable_gpio)
> > +               gpiod_set_value(boe->enable_gpio, 0);
> > +       return ret;
> > +}
> > +
> > +static int boe_panel_enable(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       int ret;
> > +
> > +       if (boe->enabled)
> > +               return 0;
> > +
> > +       ret = backlight_enable(boe->backlight);
> > +       if (ret) {
> > +               dev_err(panel->dev, "Failed to enable backlight %d\n",
> > +                       ret);
> > +               return ret;
> > +       }
> > +
> > +       boe->enabled = true;
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct drm_display_mode boe_default_mode = {
> > +       .clock = 159425,
> > +       .hdisplay = 1200,
> > +       .hsync_start = 1200 + 100,
> > +       .hsync_end = 1200 + 100 + 40,
> > +       .htotal = 1200 + 100 + 40 + 24,
> > +       .vdisplay = 1920,
> > +       .vsync_start = 1920 + 10,
> > +       .vsync_end = 1920 + 10 + 14,
> > +       .vtotal = 1920 + 10 + 14 + 4,
> > +       .vrefresh = 60,
> > +       .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> > +};
> > +
> > +static const struct panel_desc boe_tv101wum_nl6_desc = {
> > +       .modes = &boe_default_mode,
> > +       .bpc = 8,
> > +       .size = {
> > +               .width = 216,
> > +               .height = 135,

This is wrong, as this is a portrait panel, should be: width=135, height=216.

> > +       },
> > +       .lanes = 4,
> > +       .format = MIPI_DSI_FMT_RGB888,
> > +       .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> > +                     MIPI_DSI_MODE_LPM,
> > +       .init_cmds = boe_init_cmd,
> > +};
> > +
> > +static int boe_panel_get_modes(struct drm_panel *panel)
> > +{
> > +       struct boe_panel *boe = to_boe_panel(panel);
> > +       const struct drm_display_mode *m = boe->desc->modes;
> > +       struct drm_display_mode *mode;
> > +
> > +       mode = drm_mode_duplicate(panel->drm, m);
> > +       if (!mode) {
> > +               dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
> > +                       m->hdisplay, m->vdisplay, m->vrefresh);
> > +               return -ENOMEM;
> > +       }
> > +
> > +       drm_mode_set_name(mode);
> > +
>
> Sam suggested adding this here:
> mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;

Scrap that, I see that you added it in boe_default_mode.

>
> > +       drm_mode_probed_add(panel->connector, mode);
> > +
> > +       panel->connector->display_info.width_mm = boe->desc->size.width;
> > +       panel->connector->display_info.height_mm = boe->desc->size.height;
> > +       panel->connector->display_info.bpc = boe->desc->bpc;
> > +
> > +       return 1;
> > +}
> > +
> > +static const struct drm_panel_funcs boe_panel_funcs = {
> > +       .disable = boe_panel_disable,
> > +       .unprepare = boe_panel_unprepare,
> > +       .prepare = boe_panel_prepare,
> > +       .enable = boe_panel_enable,
> > +       .get_modes = boe_panel_get_modes,
> > +};
> > +
> > +static int boe_panel_add(struct boe_panel *boe)
> > +{
> > +       struct device *dev = &boe->dsi->dev;
> > +
> > +       boe->avdd = devm_regulator_get(dev, "avdd");
> > +       if (IS_ERR(boe->avdd))
> > +               return PTR_ERR(boe->avdd);
> > +
> > +       boe->avee = devm_regulator_get(dev, "avee");
> > +       if (IS_ERR(boe->avee))
> > +               return PTR_ERR(boe->avee);
> > +
> > +       boe->pp1800 = devm_regulator_get(dev, "pp1800");
> > +       if (IS_ERR(boe->pp1800))
> > +               return PTR_ERR(boe->pp1800);
> > +
> > +       boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
> > +       if (IS_ERR(boe->enable_gpio)) {
> > +               dev_err(dev, "cannot get reset-gpios %ld\n",
> > +                       PTR_ERR(boe->enable_gpio));
> > +               return PTR_ERR(boe->enable_gpio);
> > +       }
> > +
> > +       gpiod_set_value(boe->enable_gpio, 0);
> > +
> > +       boe->backlight = devm_of_find_backlight(dev);
> > +       if (IS_ERR(boe->backlight))
> > +               return PTR_ERR(boe->backlight);
> > +
> > +       drm_panel_init(&boe->base);
> > +       boe->base.funcs = &boe_panel_funcs;
> > +       boe->base.dev = &boe->dsi->dev;
> > +
> > +       return drm_panel_add(&boe->base);
> > +}
> > +
> > +static int boe_panel_probe(struct mipi_dsi_device *dsi)
> > +{
> > +       struct boe_panel *boe;
> > +       int ret;
> > +       const struct panel_desc *desc;
> > +
> > +       boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
> > +       if (!boe)
> > +               return -ENOMEM;
> > +
> > +       desc = of_device_get_match_data(&dsi->dev);
> > +       dsi->lanes = desc->lanes;
> > +       dsi->format = desc->format;
> > +       dsi->mode_flags = desc->mode_flags;
> > +       boe->desc = desc;
> > +       boe->dsi = dsi;
> > +       ret = boe_panel_add(boe);
> > +       if (ret < 0)
> > +               return ret;
> > +
> > +       mipi_dsi_set_drvdata(dsi, boe);
> > +
> > +       return mipi_dsi_attach(dsi);
> > +}
> > +
> > +static int boe_panel_remove(struct mipi_dsi_device *dsi)
> > +{
> > +       struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
> > +       int ret;
> > +
> > +       ret = boe_panel_disable(&boe->base);
> > +       if (ret < 0)
> > +               dev_err(&dsi->dev, "failed to disable panel: %d\n", ret);
> > +
> > +       ret = mipi_dsi_detach(dsi);
> > +       if (ret < 0)
> > +               dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
> > +
> > +       if (boe->base.dev)
> > +               drm_panel_remove(&boe->base);
> > +
> > +       return 0;
> > +}
> > +
> > +static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
> > +{
> > +       struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
> > +
> > +       boe_panel_disable(&boe->base);
> > +}
> > +
> > +static const struct of_device_id boe_of_match[] = {
> > +       { .compatible = "boe,tv101wum-nl6",
> > +         .data = &boe_tv101wum_nl6_desc
> > +       },
> > +       { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, boe_of_match);
> > +
> > +static struct mipi_dsi_driver boe_panel_driver = {
> > +       .driver = {
> > +               .name = "panel-boe-tv101wum-nl6",
> > +               .of_match_table = boe_of_match,
> > +       },
> > +       .probe = boe_panel_probe,
> > +       .remove = boe_panel_remove,
> > +       .shutdown = boe_panel_shutdown,
> > +};
> > +module_mipi_dsi_driver(boe_panel_driver);
> > +
> > +MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
> > +MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.21.0
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel