From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17728C433B4 for ; Thu, 15 Apr 2021 06:17:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4527A61574 for ; Thu, 15 Apr 2021 06:17:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4527A61574 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bugs.launchpad.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lWvJO-00040r-6u for qemu-devel@archiver.kernel.org; Thu, 15 Apr 2021 02:17:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lWvIG-0003Nh-R9 for qemu-devel@nongnu.org; Thu, 15 Apr 2021 02:16:00 -0400 Received: from indium.canonical.com ([91.189.90.7]:44520) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lWvI7-0002B7-31 for qemu-devel@nongnu.org; Thu, 15 Apr 2021 02:15:59 -0400 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.86_2 #2 (Debian)) id 1lWvI4-0001Fq-ME for ; Thu, 15 Apr 2021 06:15:48 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id A18A12E8157 for ; Thu, 15 Apr 2021 06:15:48 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Thu, 15 Apr 2021 06:05:02 -0000 From: Teodori Serge <1923197@bugs.launchpad.net> To: qemu-devel@nongnu.org X-Launchpad-Notification-Type: bug X-Launchpad-Bug: product=qemu; status=Invalid; importance=Undecided; assignee=None; X-Launchpad-Bug-Tags: riscv64 X-Launchpad-Bug-Information-Type: Public X-Launchpad-Bug-Private: no X-Launchpad-Bug-Security-Vulnerability: no X-Launchpad-Bug-Commenters: alistair2323 teodori-serge X-Launchpad-Bug-Reporter: Teodori Serge (teodori-serge) X-Launchpad-Bug-Modifier: Teodori Serge (teodori-serge) References: <161797335493.30650.12922009005165891710.malonedeb@gac.canonical.com> <161845970725.8931.11860624017741986671.malone@gac.canonical.com> Message-Id: Subject: Re: [Bug 1923197] Re: RISC-V priviledged instruction error X-Launchpad-Message-Rationale: Subscriber (QEMU) @qemu-devel-ml X-Launchpad-Message-For: qemu-devel-ml Precedence: bulk X-Generated-By: Launchpad (canonical.com); Revision="929bdb49da44562d032228b8f93c5c598dae8678"; Instance="production" X-Launchpad-Hash: 3ee4256aa04c466aa7c84f7549276e9ad13ca8d6 Received-SPF: none client-ip=91.189.90.7; envelope-from=bounces@canonical.com; helo=indium.canonical.com X-Spam_score_int: -65 X-Spam_score: -6.6 X-Spam_bar: ------ X-Spam_report: (-6.6 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Bug 1923197 <1923197@bugs.launchpad.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hello Francis, I'll configure PMP than do the test again. Sorry I hadn't understood what changed between version 5.2 and 6.0-rc2, since my code worked before. Best regards, Teodori Serge On Thu, 15 Apr 2021, 06:15 Alistair Francis, <1923197@bugs.launchpad.net> wrote: > I'm guessing that this is a bug in your guest as it hasn't configured > PMP regions. > > >From the RISC-V spec: > > " > If no PMP entry matches an M-mode access, the access succeeds. If no PMP > entry matches an > S-mode or U-mode access, but at least one PMP entry is implemented, the > access fails. > " > > Confusingly implemented here means implemented in hardware, not just > configured. > > ** Changed in: qemu > Status: Confirmed =3D> Invalid > > -- > You received this bug notification because you are subscribed to the bug > report. > https://bugs.launchpad.net/bugs/1923197 > > Title: > RISC-V priviledged instruction error > > To manage notifications about this bug go to: > https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions > -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1923197 Title: RISC-V priviledged instruction error Status in QEMU: Invalid Bug description: Hello when performing an MRET with MPP set to something else than 0b11 in MSTATUS, 'Invalid Instruction' exception will be triggered. The problem appeared in code after version 5.2.0. Use following code to test. =C2=A0=C2=A0# setup interrupt handling for monitor mode =C2=A0=C2=A0la t0, entry_loop =C2=A0=C2=A0la t1, entry_trap =C2=A0=C2=A0li t2, 0x888 =C2=A0=C2=A0li t3, 0x1880 =C2=A0=C2=A0csrw mepc, t0 =C2=A0=C2=A0csrw mtvec, t1 =C2=A0=C2=A0csrs mie, t2 =C2=A0=C2=A0csrs mstatus, t3 =C2=A0=C2=A0# if supervisor mode not supported, then loop forever =C2=A0=C2=A0csrr t0, misa =C2=A0=C2=A0li t1, 0x40000 =C2=A0=C2=A0and t2, t1, t0 =C2=A0=C2=A0beqz t2, 1f =C2=A0=C2=A0# setup interrupt i& exception delegation for supervisor mode =C2=A0=C2=A0li t0, 0xc0000000 # 3 GiB (entry address of supervisor) =C2=A0=C2=A0li t1, 0x1000 =C2=A0=C2=A0li t2, 0x300 =C2=A0=C2=A0li t3, 0x222 =C2=A0=C2=A0csrw mepc, t0 =C2=A0=C2=A0csrc mstatus, t1 =C2=A0=C2=A0csrs medeleg, t2 =C2=A0=C2=A0csrs mideleg, t3 =C2=A0=C2=A0# pass mhartid as first parameter to supervisor =C2=A0=C2=A0csrr a0, mhartid 1: =C2=A0=C2=A0mret To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1923197/+subscriptions