From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6550EC433E0 for ; Thu, 14 May 2020 09:29:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F3CE2065D for ; Thu, 14 May 2020 09:29:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="M+DpRLIR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726010AbgENJ3p (ORCPT ); Thu, 14 May 2020 05:29:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725878AbgENJ3p (ORCPT ); Thu, 14 May 2020 05:29:45 -0400 Received: from mail-oi1-x241.google.com (mail-oi1-x241.google.com [IPv6:2607:f8b0:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D497DC061A0C for ; Thu, 14 May 2020 02:29:44 -0700 (PDT) Received: by mail-oi1-x241.google.com with SMTP id c12so23001108oic.1 for ; Thu, 14 May 2020 02:29:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wCiVumaq6wcVuq/rN4Y5EIzrDgqgEOQzKlYptSZX3oI=; b=M+DpRLIR1KWirx3ozNZP183Wa9bvcBtupJ5hvzmrcyfFPbUkajYX+pFLOP4Vjb4X3Q FawvRVJjskYpkc8utMwVe7ZNMW2Inj1BKHHE2LnEYcmYwkWaNLk9n5d1FVKTxgNhfB3l UeLQstW6MTljDRR8YXBVCjxQJ3MgwzrCqTMcpxplnwe6OKYeQvVdg+RFBOnKN9G8xvgA YQDSlyR5MhpVKtpbxiTan5wbl1+Ib4nZ/PKuukIXE2aP2T0U5iQmkiEegUxC8DZRHHJV zrnt1YMrwrTw5F9/2w2yf3NHl+5iAs6d9DFayhdpxRNlJD8LKx0cobudOvyhGXHYb7wu gRKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wCiVumaq6wcVuq/rN4Y5EIzrDgqgEOQzKlYptSZX3oI=; b=Jz0o8wqUXt7+KVWuUpNS/mlV/vMlXehQ4zYgITrLJOnJ21br06Edz3iSVfuLLnqFeZ vO0+aWZ+y3L4FOlrythQUnWbKhotESbGXyW68rlkzbRAjB+qiVXmpS1WB6B9B9M0eMyi J43emVkeW8USU4VzY6PgupBD+8mUF9U6ervzKuvsUfZGOTrXOGpaxPLaEfsJKeLkf29/ 2NyCAczUMgEUFh0yKSKAJvxsFay4cdq7ZlKuRKTPurnyBXahXg/1w4klArlccDgkSUsw DmHn3gn9T+9DrxOXG1azCY1eO4w1qmfz+oUAHG/uYBGBJo41ytSfIPHIm5w4Fy8xtbrf aUTw== X-Gm-Message-State: AOAM530QziVwK+19N9uILJwJfqwQdthm5FqXMol27X4TonjD33rm+xzm xLWc6xRHwIX13lRNk6p293ovjKOE7QbTTj9MpQHhcg== X-Google-Smtp-Source: ABdhPJy0BZy/80kBmbbNGXWB+0otugy/D99TGiabeb7uQ63D/N2iRHOx8D9HzC8UVf8RQ4g/SJRNWcVVjR51nBt0dp4= X-Received: by 2002:aca:3585:: with SMTP id c127mr4674008oia.32.1589448584196; Thu, 14 May 2020 02:29:44 -0700 (PDT) MIME-Version: 1.0 References: <20200514060243.106976-1-zong.li@sifive.com> In-Reply-To: <20200514060243.106976-1-zong.li@sifive.com> From: Zong Li Date: Thu, 14 May 2020 17:29:33 +0800 Message-ID: Subject: Re: [PATCH] riscv: perf: fix build error for dependency issue To: Paul Walmsley , Palmer Dabbelt , Andrew Morton , linux-riscv , "linux-kernel@vger.kernel.org List" , Kefeng Wang Cc: Greentime Hu Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 14, 2020 at 2:03 PM Zong Li wrote: > > CONFIG_RISCV_BASE_PMU can be selected or unselected, but in fact, > CONFIG_RISCV_BASE_PMU must be always selected when selecting > CONFIG_PERF_EVENTS on current perf implementation, otherwise, it > would cause the build error when only selecting CONFIG_PERF_EVENTS. > The build case is applied randconfig which generated by kbuild test. > > This patch removes the unnecessary configuration and implementations. > Eventually, the number of counters should be determinated at runtime, > such as DTB, so we don't need to re-build kernel for various platform > which has got different number of hpmcounters. > > Signed-off-by: Zong Li > Signed-off-by: Greentime Hu > --- > arch/riscv/Kconfig | 13 ------------- > arch/riscv/include/asm/perf_event.h | 16 +++------------- > 2 files changed, 3 insertions(+), 26 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 74f82cf4f781..7d5123576953 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -283,19 +283,6 @@ config RISCV_ISA_C > > If you don't know what to do here, say Y. > > -menu "supported PMU type" > - depends on PERF_EVENTS > - > -config RISCV_BASE_PMU > - bool "Base Performance Monitoring Unit" > - def_bool y > - help > - A base PMU that serves as a reference implementation and has limited > - feature of perf. It can run on any RISC-V machines so serves as the > - fallback, but this option can also be disable to reduce kernel size. > - > -endmenu > - > config FPU > bool "FPU support" > default y > diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h > index 0234048b12bc..8e5b1d81112c 100644 > --- a/arch/riscv/include/asm/perf_event.h > +++ b/arch/riscv/include/asm/perf_event.h > @@ -16,15 +16,11 @@ > > /* > * The RISCV_MAX_COUNTERS parameter should be specified. > + * Currently, we only support base PMU, so just make > + * RISCV_MAX_COUNTERS be equal to RISCV_BASE_COUNTERS. > */ > > -#ifdef CONFIG_RISCV_BASE_PMU > -#define RISCV_MAX_COUNTERS 2 > -#endif > - > -#ifndef RISCV_MAX_COUNTERS > -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." > -#endif > +#define RISCV_MAX_COUNTERS RISCV_BASE_COUNTERS > > /* > * These are the indexes of bits in counteren register *minus* 1, > @@ -38,12 +34,6 @@ > */ > #define RISCV_PMU_CYCLE 0 > #define RISCV_PMU_INSTRET 1 > -#define RISCV_PMU_MHPMCOUNTER3 2 > -#define RISCV_PMU_MHPMCOUNTER4 3 > -#define RISCV_PMU_MHPMCOUNTER5 4 > -#define RISCV_PMU_MHPMCOUNTER6 5 > -#define RISCV_PMU_MHPMCOUNTER7 6 > -#define RISCV_PMU_MHPMCOUNTER8 7 > > #define RISCV_OP_UNSUPP (-EOPNOTSUPP) > > -- > 2.26.2 > Hi all, I don't notice that there was a patch already to fix this issue by Kefeng, (https://lore.kernel.org/linux-riscv/mhng-58148e77-03b6-4c56-98ea-0d0cbf99d522@palmerdabbelt-glaptop1/T/#u). Even though it was a different way, but I also think it was good for the present. As my comment in this patch, eventually, the number of counters should be decided at runtime, such as DTB, then we don't need to re-build kernel for various platform which has got a different number of hpmcounters. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1CB0C433E0 for ; Thu, 14 May 2020 09:29:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB67A2065D for ; Thu, 14 May 2020 09:29:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="L8/G+Ni2"; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wCiVumaq6wcVuq/rN4Y5EIzrDgqgEOQzKlYptSZX3oI=; b=Rl3zrzbsQRTsGkrlNN5wqu06NTvCkP6lpTaCLJlaYn6mAawz6KED0lYOrkKsCfD3yl 5tkSVhPX0WkpVkcAyUYxQB5/7bA9F/GLkopkXE7XIFmmXuzkvrGFoYOQ82f7IgafqTEH MeS8Va15E4wFgsXQLmrIZbNQGjDfdpj41AUwzdzTr6fY/CksF5qmZ+clp0vv1t6LZ68j 6T453f6j31UqIUTFxfH4kEHDrp5NXyQzGKCN5NM9mHI/bQGxla2g3uzirjOtP2iBNsfL QDuvkyuvKnGQ9h7fw3nKlJzjHIMIi09bot6M8wHOk5mcCk/TLiqnbGL99jpFZImNBinZ sX4w== X-Gm-Message-State: AOAM5320KzuU555jbkkqhPADrGpwVi57+i+w3icriDCB+09iQWi4SjPX WamEDye2BRrJt7VFEqrHwUYNbNr41TLgEIemPydf2+ism4g= X-Google-Smtp-Source: ABdhPJy0BZy/80kBmbbNGXWB+0otugy/D99TGiabeb7uQ63D/N2iRHOx8D9HzC8UVf8RQ4g/SJRNWcVVjR51nBt0dp4= X-Received: by 2002:aca:3585:: with SMTP id c127mr4674008oia.32.1589448584196; Thu, 14 May 2020 02:29:44 -0700 (PDT) MIME-Version: 1.0 References: <20200514060243.106976-1-zong.li@sifive.com> In-Reply-To: <20200514060243.106976-1-zong.li@sifive.com> From: Zong Li Date: Thu, 14 May 2020 17:29:33 +0800 Message-ID: Subject: Re: [PATCH] riscv: perf: fix build error for dependency issue To: Paul Walmsley , Palmer Dabbelt , Andrew Morton , linux-riscv , "linux-kernel@vger.kernel.org List" , Kefeng Wang Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200514_022946_500997_B9347106 X-CRM114-Status: GOOD ( 23.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Greentime Hu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, May 14, 2020 at 2:03 PM Zong Li wrote: > > CONFIG_RISCV_BASE_PMU can be selected or unselected, but in fact, > CONFIG_RISCV_BASE_PMU must be always selected when selecting > CONFIG_PERF_EVENTS on current perf implementation, otherwise, it > would cause the build error when only selecting CONFIG_PERF_EVENTS. > The build case is applied randconfig which generated by kbuild test. > > This patch removes the unnecessary configuration and implementations. > Eventually, the number of counters should be determinated at runtime, > such as DTB, so we don't need to re-build kernel for various platform > which has got different number of hpmcounters. > > Signed-off-by: Zong Li > Signed-off-by: Greentime Hu > --- > arch/riscv/Kconfig | 13 ------------- > arch/riscv/include/asm/perf_event.h | 16 +++------------- > 2 files changed, 3 insertions(+), 26 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 74f82cf4f781..7d5123576953 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -283,19 +283,6 @@ config RISCV_ISA_C > > If you don't know what to do here, say Y. > > -menu "supported PMU type" > - depends on PERF_EVENTS > - > -config RISCV_BASE_PMU > - bool "Base Performance Monitoring Unit" > - def_bool y > - help > - A base PMU that serves as a reference implementation and has limited > - feature of perf. It can run on any RISC-V machines so serves as the > - fallback, but this option can also be disable to reduce kernel size. > - > -endmenu > - > config FPU > bool "FPU support" > default y > diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h > index 0234048b12bc..8e5b1d81112c 100644 > --- a/arch/riscv/include/asm/perf_event.h > +++ b/arch/riscv/include/asm/perf_event.h > @@ -16,15 +16,11 @@ > > /* > * The RISCV_MAX_COUNTERS parameter should be specified. > + * Currently, we only support base PMU, so just make > + * RISCV_MAX_COUNTERS be equal to RISCV_BASE_COUNTERS. > */ > > -#ifdef CONFIG_RISCV_BASE_PMU > -#define RISCV_MAX_COUNTERS 2 > -#endif > - > -#ifndef RISCV_MAX_COUNTERS > -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." > -#endif > +#define RISCV_MAX_COUNTERS RISCV_BASE_COUNTERS > > /* > * These are the indexes of bits in counteren register *minus* 1, > @@ -38,12 +34,6 @@ > */ > #define RISCV_PMU_CYCLE 0 > #define RISCV_PMU_INSTRET 1 > -#define RISCV_PMU_MHPMCOUNTER3 2 > -#define RISCV_PMU_MHPMCOUNTER4 3 > -#define RISCV_PMU_MHPMCOUNTER5 4 > -#define RISCV_PMU_MHPMCOUNTER6 5 > -#define RISCV_PMU_MHPMCOUNTER7 6 > -#define RISCV_PMU_MHPMCOUNTER8 7 > > #define RISCV_OP_UNSUPP (-EOPNOTSUPP) > > -- > 2.26.2 > Hi all, I don't notice that there was a patch already to fix this issue by Kefeng, (https://lore.kernel.org/linux-riscv/mhng-58148e77-03b6-4c56-98ea-0d0cbf99d522@palmerdabbelt-glaptop1/T/#u). Even though it was a different way, but I also think it was good for the present. As my comment in this patch, eventually, the number of counters should be decided at runtime, such as DTB, then we don't need to re-build kernel for various platform which has got a different number of hpmcounters.