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Tue, 31 Aug 2021 19:50:30 -0700 (PDT) MIME-Version: 1.0 References: <20210831092038.21669-1-zong.li@sifive.com> <20210831092038.21669-3-zong.li@sifive.com> In-Reply-To: From: Zong Li Date: Wed, 1 Sep 2021 10:50:18 +0800 Message-ID: Subject: Re: [PATCH v4 2/4] riscv: lib: implement enable_caches for sifive cache To: Rick Chen Cc: U-Boot Mailing List , rick , Leo Liang , Sean Anderson , Bin Meng , Green Wan , Paul Walmsley , Simon Glass Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Wed, Sep 1, 2021 at 10:06 AM Rick Chen wrote: > > > From: Zong Li > > Sent: Tuesday, August 31, 2021 5:21 PM > > To: Rick Jian-Zhi Chen(=E9=99=B3=E5=BB=BA=E5=BF=97) ; Leo Yu-Chi Liang(=E6=A2=81=E8=82=B2=E9=BD=8A) ; b= meng.cn@gmail.com; seanga2@gmail.com; green.wan@sifive.com; paul.walmsley@s= ifive.com; sjg@chromium.org; u-boot@lists.denx.de > > Cc: Zong Li > > Subject: [PATCH v4 2/4] riscv: lib: implement enable_caches for sifive = cache > > > > The enable_caches is a generic hook for architecture-implemented, we de= fine this function to enable composable cache of sifive platforms. > > > > In sifive_cache, it invokes the generic cache_enable interface of cache= uclass to execute the relative implementation in SiFive ccache driver. > > > > Signed-off-by: Zong Li > > --- > > arch/riscv/Kconfig | 5 +++++ > > arch/riscv/lib/Makefile | 1 + > > arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++ > > common/board_r.c | 4 ++-- > > 4 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 = arch/riscv/lib/sifive_cache.c > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3dffa6..= ec651fe0a4 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT > > The SiFive CLINT block holds memory-mapped control and status= registers > > associated with software and timer interrupts. > > > > +config SIFIVE_CACHE > > + bool > > + help > > + This enables the operations to configure SiFive cache > > + > > config ANDES_PLIC > > bool > > depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/ris= cv/lib/Makefile b/arch/riscv/lib/Makefile index c4cc41434b..06020fcc2a 1006= 44 > > --- a/arch/riscv/lib/Makefile > > +++ b/arch/riscv/lib/Makefile > > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) +=3D bootm.o > > obj-$(CONFIG_CMD_BOOTI) +=3D bootm.o image.o > > obj-$(CONFIG_CMD_GO) +=3D boot.o > > obj-y +=3D cache.o > > +obj-$(CONFIG_SIFIVE_CACHE) +=3D sifive_cache.o > > ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) > > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) +=3D sifive_clint.o > > obj-$(CONFIG_ANDES_PLIC) +=3D andes_plic.o diff --git a/arch/riscv/lib= /sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file mode 100644 index = 0000000000..28154878fc > > --- /dev/null > > +++ b/arch/riscv/lib/sifive_cache.c > > @@ -0,0 +1,27 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2021 SiFive, Inc > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +void enable_caches(void) > > +{ > > + struct udevice *dev; > > + int ret; > > + > > + /* Enable ways of ccache */ > > + ret =3D uclass_get_device_by_driver(UCLASS_CACHE, > > + DM_DRIVER_GET(sifive_ccache), > > + &dev); > > + if (ret) { > > + log_debug("Cannot enable cache ways"); > > + } else { > > + ret =3D cache_enable(dev); > > + if (ret) > > + log_debug("ccache enable failed"); > > + } > > +} > > diff --git a/common/board_r.c b/common/board_r.c index e3e6248a1f..630c= 2451a2 100644 > > --- a/common/board_r.c > > +++ b/common/board_r.c > > @@ -114,7 +114,7 @@ static int initr_reloc(void) > > return 0; > > } > > > > -#ifdef CONFIG_ARM > > +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) > > Here may cause other RISC-V platforms build error. > eq, ae350 will compile error as below: > common/board_r.o: in function `initr_caches': > /u-boot-riscv/common/board_r.c:124: undefined reference to `enable_caches= ' > Makefile:1795: recipe for target 'u-boot' failed > > Maybe you can separate this part an isolate patch: > board_r: enable initr_caches for RISC-V ... > And also implement the week function for others. > Thanks for reviewing that. I would fix it and send the next version. > Thanks, > Rick > > > > > /* > > * Some of these functions are needed purely because the functions the= y > > * call return void. If we change them to return 0, these stubs can go= away. > > @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] =3D { > > initr_trace, > > initr_reloc, > > /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFI= G_ARM > > +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) > > initr_caches, > > /* Note: For Freescale LS2 SoCs, new MMU table is created in DD= R. > > * A temporary mapping of IFC high region is since remove= d, > > -- > > 2.32.0