From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65B2DC63697 for ; Mon, 23 Nov 2020 07:18:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E7B720738 for ; Mon, 23 Nov 2020 07:18:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="Nhi41X2p" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727641AbgKWHS3 (ORCPT ); Mon, 23 Nov 2020 02:18:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726921AbgKWHS2 (ORCPT ); Mon, 23 Nov 2020 02:18:28 -0500 Received: from mail-ot1-x341.google.com (mail-ot1-x341.google.com [IPv6:2607:f8b0:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45845C061A4D for ; Sun, 22 Nov 2020 23:18:28 -0800 (PST) Received: by mail-ot1-x341.google.com with SMTP id f12so3564797oto.10 for ; Sun, 22 Nov 2020 23:18:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sfKjG2GvoDhQiB7EpkscGKZ+97rkBF/pnq0LhdxYBSQ=; b=Nhi41X2pbTeawhTkWHetJJ8SzZ7jdWhXuzFPECnPqfmjT2n5H0aJE/I9Fhz5WpkOTi U1f2uuCWR5MWR2ZUnRWcMSrmka1wwVzu4a6pwiYKsFabNZqQNgXJiJtVdQg6fBKG/ojv wQoiop9+kZRRADXjWOAF/gd5OO+gMdZdnWewS7O9jsEwzxEuyzSYSbmjWGXuCLu3smeQ aS/po47CbgOhCG5PUD2dzUI/mjZVLQVhLYtj9N8+Ga+eh9ixBzz4dcx2Roiqpt4QI0Al kmDFP01bTVN1xbUdqzWFwfsEyaL8LjqdkSyLMg1fWWx/9PneRe4zhP1jMIaBy3BPBPMv 92TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=sfKjG2GvoDhQiB7EpkscGKZ+97rkBF/pnq0LhdxYBSQ=; b=CTIRnaRIvAvuxd8NG4IpSbUZu25t7pzqxvksZHzBPDTFOp93qUSF1Adj8gUe3plV91 pL+pJwoVtEbgUMGNvIH3wWzTC8pwUA6yNDmpjYJH3zE4YXF0PMJFF8nLnmAg+ZXMrHCl 5kzMmXgHP+ojJiOoOJ7YDL7/lh7UrpGoy0Q8HIkJWP3/PKb0xGPMmY27huzTMu7oORPO /w5Yak9gLoZsEYp/mF4QeX5aPK0Vj26H8lx2nVHQgBTYWGJABAhHIXBRcZvdmCU68IdU G0C8LPy4MDgFpE/c78iRcXExtO+N4e0P3fpWfcsZBKy/LS8UouBbj7Pw9y37EnXWTFsu mh8g== X-Gm-Message-State: AOAM532BYcmRBs7JQ8vCLElqV50VX5REoDcxZx7DvS8QtGXWEe9NwTgt FvxPtSM3zgMRbz4//0Y1RhE6JFukI1feCEPjQQYTRA== X-Google-Smtp-Source: ABdhPJweIoXhEjpbvXwglI32aXPOWNF6IbolZiWACHGNa+GuXDBW2FXTa0dak0WYveQO8IuYFPBrvHcq4162/Q4SUIA= X-Received: by 2002:a9d:6f8f:: with SMTP id h15mr22428460otq.166.1606115907677; Sun, 22 Nov 2020 23:18:27 -0800 (PST) MIME-Version: 1.0 References: <20201111100608.108842-5-zong.li@sifive.com> In-Reply-To: From: Zong Li Date: Mon, 23 Nov 2020 15:18:17 +0800 Message-ID: Subject: Re: [PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift To: Palmer Dabbelt Cc: Paul Walmsley , Stephen Boyd , Andreas Schwab , Pragnesh Patel , Albert Ou , Michael Turquette , Yash Shah , "linux-kernel@vger.kernel.org List" , linux-clk@vger.kernel.org, linux-riscv , Pragnesh Patel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote: > > On Wed, 11 Nov 2020 02:06:08 PST (-0800), zong.li@sifive.com wrote: > > The clk enable bit should be 31 instead of 24. > > > > Signed-off-by: Zong Li > > Reported-by: Pragnesh Patel > > --- > > drivers/clk/sifive/sifive-prci.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h > > index 802fc8fb9c09..da7be9103d4d 100644 > > --- a/drivers/clk/sifive/sifive-prci.h > > +++ b/drivers/clk/sifive/sifive-prci.h > > @@ -59,7 +59,7 @@ > > > > /* DDRPLLCFG1 */ > > #define PRCI_DDRPLLCFG1_OFFSET 0x10 > > -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 > > +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 > > #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) > > > > /* GEMGXLPLLCFG0 */ > > @@ -81,7 +81,7 @@ > > > > /* GEMGXLPLLCFG1 */ > > #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 > > -#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 24 > > +#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 31 > > #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) > > > > /* CORECLKSEL */ > > Section 7.3 of v1.0 of the FU540 manual says that bit 24 contains the PLL clock > enable for both of these. I don't know if that's accurate, but if it is then I > believe this would break the FU540. Don't have one to test on, though. Yes, the manual seems to be wrong and should be corrected. It doesn't break the FU540 yet because we don't use these fields in s-mode Linux driver, we set them in m-mode FSBL/U-boot-SPL bootloader during boot time, and the implementation of FSBL and U-boot-SPL both are correct. The following link is the U-boot SPL source: https://github.com/u-boot/u-boot/blob/da09b99ea572cec9a114872e480b798db11f9c6e/drivers/clk/sifive/fu540-prci.c#L128 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F119C2D0E4 for ; Mon, 23 Nov 2020 07:18:41 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 985182072C for ; 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Sun, 22 Nov 2020 23:18:27 -0800 (PST) MIME-Version: 1.0 References: <20201111100608.108842-5-zong.li@sifive.com> In-Reply-To: From: Zong Li Date: Mon, 23 Nov 2020 15:18:17 +0800 Message-ID: Subject: Re: [PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift To: Palmer Dabbelt X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201123_021829_368672_84D13A70 X-CRM114-Status: GOOD ( 18.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Stephen Boyd , Michael Turquette , "linux-kernel@vger.kernel.org List" , Pragnesh Patel , Yash Shah , Andreas Schwab , Paul Walmsley , linux-riscv , linux-clk@vger.kernel.org, Pragnesh Patel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote: > > On Wed, 11 Nov 2020 02:06:08 PST (-0800), zong.li@sifive.com wrote: > > The clk enable bit should be 31 instead of 24. > > > > Signed-off-by: Zong Li > > Reported-by: Pragnesh Patel > > --- > > drivers/clk/sifive/sifive-prci.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h > > index 802fc8fb9c09..da7be9103d4d 100644 > > --- a/drivers/clk/sifive/sifive-prci.h > > +++ b/drivers/clk/sifive/sifive-prci.h > > @@ -59,7 +59,7 @@ > > > > /* DDRPLLCFG1 */ > > #define PRCI_DDRPLLCFG1_OFFSET 0x10 > > -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24 > > +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 > > #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) > > > > /* GEMGXLPLLCFG0 */ > > @@ -81,7 +81,7 @@ > > > > /* GEMGXLPLLCFG1 */ > > #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 > > -#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 24 > > +#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 31 > > #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) > > > > /* CORECLKSEL */ > > Section 7.3 of v1.0 of the FU540 manual says that bit 24 contains the PLL clock > enable for both of these. I don't know if that's accurate, but if it is then I > believe this would break the FU540. Don't have one to test on, though. Yes, the manual seems to be wrong and should be corrected. It doesn't break the FU540 yet because we don't use these fields in s-mode Linux driver, we set them in m-mode FSBL/U-boot-SPL bootloader during boot time, and the implementation of FSBL and U-boot-SPL both are correct. The following link is the U-boot SPL source: https://github.com/u-boot/u-boot/blob/da09b99ea572cec9a114872e480b798db11f9c6e/drivers/clk/sifive/fu540-prci.c#L128 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv