From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754556AbcGEKHY (ORCPT ); Tue, 5 Jul 2016 06:07:24 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:36790 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754153AbcGEKHX (ORCPT ); Tue, 5 Jul 2016 06:07:23 -0400 MIME-Version: 1.0 In-Reply-To: References: <1466856870-17153-1-git-send-email-prasannatsmkumar@gmail.com> From: PrasannaKumar Muralidharan Date: Tue, 5 Jul 2016 15:37:21 +0530 Message-ID: Subject: Re: [RFC] mips: Add MXU context switching support To: "Maciej W. Rozycki" Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexey Dobriyan , John Stultz , mguzik@redhat.com, athorlton@sgi.com, mhocko@suse.com, ebiederm@xmission.com, gorcunov@openvz.org, luto@kernel.org, cl@linux.com, serge.hallyn@ubuntu.com, Kees Cook , jslaby@suse.cz, Andrew Morton , Florian Fainelli , mingo@kernel.org, alex.smith@imgtec.com, markos.chandras@imgtec.com, Leonid Yegoshin , david.daney@cavium.com, zhaoxiu.zeng@gmail.com, chenhc@lemote.com, Zubair.Kakakhel@imgtec.com, James Hogan , Paul Burton , Ralf Baechle Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5 July 2016 at 04:00, Maciej W. Rozycki wrote: > On Sat, 25 Jun 2016, PrasannaKumar Muralidharan wrote: > >> diff --git a/arch/mips/include/asm/mxu.h b/arch/mips/include/asm/mxu.h >> new file mode 100644 >> index 0000000..cf77cbd >> --- /dev/null >> +++ b/arch/mips/include/asm/mxu.h >> @@ -0,0 +1,157 @@ >> +/* >> + * Copyright (C) Ingenic Semiconductor >> + * File taken from Ingenic Semiconductor's linux repo available in github >> + * >> + * This program is free software; you can redistribute it and/or modify it >> + * under the terms of the GNU General Public License as published by the >> + * Free Software Foundation; either version 2 of the License, or (at your >> + * option) any later version. >> + */ >> +#ifndef _ASM_MXU_H >> +#define _ASM_MXU_H >> + >> +#include >> +#include >> +#include >> +#include >> + >> +static inline void __enable_mxu(void) >> +{ >> + unsigned int register val asm("t0"); >> + val = 3; >> + asm volatile(".word 0x7008042f\n\t"::"r"(val)); > > Can you please document your manually generated machine code, i.e. what > instruction 0x7008042f actually is? I have taken this header from vendor kernel. This instruction saves 3 to xr16 register. I will document them in the next revision. > Also our convention has been to separate asm operands with spaces, and > there's no need for a new line or a tab character at the end of an > inline as GCC will add these automatically as needed, i.e.: > > asm volatile(".word 0x7008042f" : : "r" (val)); > > Likewise throughout. Will follow the convention. >> +static inline void __save_mxu(void *tsk_void) >> +{ >> + struct task_struct *tsk = tsk_void; >> + >> + register unsigned int reg_val asm("t0"); >> + >> + asm volatile(".word 0x7008042e\n\t"); >> + tsk->thread.mxu.xr[0] = reg_val; >> + asm volatile(".word 0x7008006e\n\t"); >> + tsk->thread.mxu.xr[1] = reg_val; >> + asm volatile(".word 0x700800ae\n\t"); >> + tsk->thread.mxu.xr[2] = reg_val; >> + asm volatile(".word 0x700800ee\n\t"); >> + tsk->thread.mxu.xr[3] = reg_val; >> + asm volatile(".word 0x7008012e\n\t"); >> + tsk->thread.mxu.xr[4] = reg_val; >> + asm volatile(".word 0x7008016e\n\t"); >> + tsk->thread.mxu.xr[5] = reg_val; >> + asm volatile(".word 0x700801ae\n\t"); >> + tsk->thread.mxu.xr[6] = reg_val; >> + asm volatile(".word 0x700801ee\n\t"); >> + tsk->thread.mxu.xr[7] = reg_val; >> + asm volatile(".word 0x7008022e\n\t"); >> + tsk->thread.mxu.xr[8] = reg_val; >> + asm volatile(".word 0x7008026e\n\t"); >> + tsk->thread.mxu.xr[9] = reg_val; >> + asm volatile(".word 0x700802ae\n\t"); >> + tsk->thread.mxu.xr[10] = reg_val; >> + asm volatile(".word 0x700802ee\n\t"); >> + tsk->thread.mxu.xr[11] = reg_val; >> + asm volatile(".word 0x7008032e\n\t"); >> + tsk->thread.mxu.xr[12] = reg_val; >> + asm volatile(".word 0x7008036e\n\t"); >> + tsk->thread.mxu.xr[13] = reg_val; >> + asm volatile(".word 0x700803ae\n\t"); >> + tsk->thread.mxu.xr[14] = reg_val; >> + asm volatile(".word 0x700803ee\n\t"); >> + tsk->thread.mxu.xr[15] = reg_val; >> +} > > Not using an output operand with asms here? I think the instruction saves the xr* register value to reg_val without need for output operand. Thanks for your review, appreciate it.