From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Wood <thomas.wood@intel.com>
Subject: Re: [PATCH 11/89 v2] drm/i915/skl: Framebuffers need to
 be aligned to 256KB on Skylake
Date: Fri, 19 Sep 2014 14:46:14 +0100
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To: Damien Lespiau <damien.lespiau@intel.com>
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On 19 September 2014 12:26, Damien Lespiau <damien.lespiau@intel.com> wrote:
> v2: Also align X tiled fbs to 256KB (Thomas)
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Thomas Wood <thomas.wood@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cf51704..a48a2f3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2182,7 +2182,9 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
>
>         switch (obj->tiling_mode) {
>         case I915_TILING_NONE:
> -               if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
> +               if (INTEL_INFO(dev)->gen >= 9)
> +                       alignment = 256 * 1024;
> +               else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
>                         alignment = 128 * 1024;
>                 else if (INTEL_INFO(dev)->gen >= 4)
>                         alignment = 4 * 1024;
> @@ -2190,8 +2192,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
>                         alignment = 64 * 1024;
>                 break;
>         case I915_TILING_X:
> -               /* pin() will align the object as required by fence */
> -               alignment = 0;
> +               if (INTEL_INFO(dev)->gen >= 9)
> +                       alignment = 256 * 1024;
> +               else {
> +                       /* pin() will align the object as required by fence */
> +                       alignment = 0;
> +               }
>                 break;
>         case I915_TILING_Y:
>                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
> --
> 1.8.3.1
>