[U-Boot] [PATCH v3 1/5] sunxi: R40: add gigabit ethernet clocks

[Joe Hershberger <joe.hershberger@ni.com>]

On Mon, Apr 23, 2018 at 9:57 AM, Lothar Felten <lothar.felten@gmail.com> wrote:
> Add clock control entries for the gigabit interface of the Allwinner
> R40/V40 CPU
>
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>

You dropped Maxime's Acks when you sent the v3. You need to include
any acks or reviews you already got in the new version unless the
patch is substantially different.

You should use tools/patman/patman and indicate any changes using the
"Series-changes: n" tags.

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

> ---
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index d35aa479f7..3ea473c302 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -61,7 +61,11 @@ struct sunxi_ccm_reg {
>         u32 reserved11;
>         u32 sata_clk_cfg;       /* 0xc8 SATA clock control (R40 only) */
>         u32 usb_clk_cfg;        /* 0xcc USB clock control */
> -       u32 gmac_clk_cfg;       /* 0xd0 GMAC clock control */
> +#ifdef CONFIG_MACH_SUN8I_R40
> +       u32 cir0_clk_cfg;       /* 0xd0 CIR0 clock control (R40 only) */
> +#else
> +       u32 gmac_clk_cfg;       /* 0xd0 GMAC clock control (not for R40) */
> +#endif
>         u32 reserved12[7];
>         u32 mdfs_clk_cfg;       /* 0xf0 MDFS clock control */
>         u32 dram_clk_cfg;       /* 0xf4 DRAM configuration clock control */
> @@ -104,7 +108,11 @@ struct sunxi_ccm_reg {
>         u32 mtc_clk_cfg;        /* 0x158 MTC module clock */
>         u32 mbus0_clk_cfg;      /* 0x15c MBUS0 module clock */
>         u32 mbus1_clk_cfg;      /* 0x160 MBUS1 module clock */
> +#ifdef CONFIG_MACH_SUN8I_R40
> +       u32 gmac_clk_cfg;       /* 0x164 GMAC clock control (R40 only) */
> +#else
>         u32 reserved16;
> +#endif
>         u32 mipi_dsi_clk_cfg;   /* 0x168 MIPI DSI clock control */
>         u32 mipi_csi_clk_cfg;   /* 0x16c MIPI CSI clock control */
>         u32 reserved17[4];
> --
> 2.14.1
>
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