[U-Boot] [PATCH] drivers: net: fsl_enetc: add support for SGMII 2500

* [U-Boot] [PATCH] drivers: net: fsl_enetc: add support for SGMII 2500
@ 2019-07-15  8:48 Alex Marginean
  2019-07-22 23:33 ` Joe Hershberger
  2019-07-25 18:41 ` [U-Boot] " Joe Hershberger
  0 siblings, 2 replies; 4+ messages in thread
From: Alex Marginean @ 2019-07-15  8:48 UTC (permalink / raw)
  To: u-boot

SGMII 2500 as supported on NXP SoCs requires AN to be disabled, handle
this case in the enetc sgmii init code.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
---

Depends on: https://patchwork.ozlabs.org/project/uboot/list/?series=117513

 drivers/net/fsl_enetc.c | 24 +++++++++++++++++++-----
 drivers/net/fsl_enetc.h |  6 ++++--
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index da533a1e5d..e7c5062c39 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -69,13 +69,25 @@ static bool enetc_has_imdio(struct udevice *dev)
 static int enetc_init_sgmii(struct udevice *dev)
 {
 	struct enetc_priv *priv = dev_get_priv(dev);
+	bool is2500 = false;
+	u16 reg;
 
 	if (!enetc_has_imdio(dev))
 		return 0;
 
-	/* Set to SGMII mode, use AN */
+	if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
+		is2500 = true;
+
+	/*
+	 * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
+	 * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
+	 * on PLL configuration.  Setting 1G for 2.5G here is counter intuitive
+	 * but intentional.
+	 */
+	reg = ENETC_PCS_IF_MODE_SGMII;
+	reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
 	enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
-			 ENETC_PCS_IF_MODE, ENETC_PCS_IF_MODE_SGMII_AN);
+			 ENETC_PCS_IF_MODE, reg);
 
 	/* Dev ability - SGMII */
 	enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
@@ -87,10 +99,11 @@ static int enetc_init_sgmii(struct udevice *dev)
 	enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
 			 ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
 
+	reg = ENETC_PCS_CR_DEF_VAL;
+	reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
 	/* restart PCS AN */
 	enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
-			 ENETC_PCS_CR,
-			 ENETC_PCS_CR_RESET_AN | ENETC_PCS_CR_DEF_VAL);
+			 ENETC_PCS_CR, reg);
 
 	return 0;
 }
@@ -130,7 +143,7 @@ static int enetc_init_sxgmii(struct udevice *dev)
 	/* Restart PCS AN */
 	enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
 			 ENETC_PCS_CR,
-			 ENETC_PCS_CR_LANE_RESET | ENETC_PCS_CR_RESET_AN);
+			 ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
 
 	return 0;
 }
@@ -174,6 +187,7 @@ static void enetc_start_pcs(struct udevice *dev)
 
 	switch (priv->if_type) {
 	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_SGMII_2500:
 		enetc_init_sgmii(dev);
 		break;
 	case PHY_INTERFACE_MODE_RGMII:
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
index 7ac7c1fefe..0bb4cdff47 100644
--- a/drivers/net/fsl_enetc.h
+++ b/drivers/net/fsl_enetc.h
@@ -183,7 +183,7 @@ struct enetc_priv {
 #define ENETC_PCS_CR			0x00
 #define  ENETC_PCS_CR_RESET_AN		0x1200
 #define  ENETC_PCS_CR_DEF_VAL		0x0140
-#define  ENETC_PCS_CR_LANE_RESET	0x8000
+#define  ENETC_PCS_CR_RST		BIT(15)
 #define ENETC_PCS_DEV_ABILITY		0x04
 #define  ENETC_PCS_DEV_ABILITY_SGMII	0x4001
 #define  ENETC_PCS_DEV_ABILITY_SXGMII	0x5001
@@ -192,7 +192,9 @@ struct enetc_priv {
 #define ENETC_PCS_LINK_TIMER2		0x13
 #define  ENETC_PCS_LINK_TIMER2_VAL	0x0003
 #define ENETC_PCS_IF_MODE		0x14
-#define  ENETC_PCS_IF_MODE_SGMII_AN	0x0003
+#define  ENETC_PCS_IF_MODE_SGMII	BIT(0)
+#define  ENETC_PCS_IF_MODE_SGMII_AN	BIT(1)
+#define  ENETC_PCS_IF_MODE_SPEED_1G	BIT(3)
 
 /* PCS replicator block for USXGMII */
 #define ENETC_PCS_DEVAD_REPL		0x1f
-- 
2.17.1

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