From mboxrd@z Thu Jan  1 00:00:00 1970
From: Joe Hershberger <joe.hershberger@ni.com>
Date: Fri, 1 Mar 2019 21:12:01 +0000
Subject: [U-Boot] [PATCH v3 11/13] clk: sunxi: h3: Implement EPHY CLK
 and RESET
In-Reply-To: <20190227185701.15545-12-jagan@amarulasolutions.com>
References: <20190227185701.15545-1-jagan@amarulasolutions.com>
 <20190227185701.15545-12-jagan@amarulasolutions.com>
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On Wed, Feb 27, 2019 at 1:02 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> EPHY CLK and RESET is available in Allwinner H3 EMAC
> via mdio-mux node of internal PHY. Add the respetive

Please fix typo in log above. respetive -> respective

> clock and reset reg and bits.
>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>