On Thu, Apr 14, 2022 at 11:57 PM Niklas Cassel via <qemu-devel@nongnu.org>
wrote:

> The device tree property "mmu-type" is currently exported as either
> "riscv,sv32" or "riscv,sv48".
>
> However, the riscv cpu device tree binding [1] has a specific value
> "riscv,none" for a HART without a MMU.
>
> Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
> option is disabled using rv32,mmu=off or rv64,mmu=off.
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
>
> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
> ---
>  hw/riscv/virt.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index da50cbed43..3be6be9ad3 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -230,8 +230,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,
> int socket,
>          cpu_name = g_strdup_printf("/cpus/cpu@%d",
>              s->soc[socket].hartid_base + cpu);
>          qemu_fdt_add_subnode(mc->fdt, cpu_name);
> -        qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
> -            (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
> +        if (riscv_feature(&s->soc[socket].harts[cpu].env,
> +                          RISCV_FEATURE_MMU)) {
> +            qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
> +                                    (is_32_bit) ? "riscv,sv32" :
> "riscv,sv48");
> +        } else {
> +            qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
> +                                    "riscv,none");
> +        }
>          name = riscv_isa_string(&s->soc[socket].harts[cpu]);
>          qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
>          g_free(name);
> --
> 2.35.1
>
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>