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[209.85.216.53]) by smtp.gmail.com with ESMTPSA id z27sm10872216pfg.91.2021.06.27.01.23.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Jun 2021 01:23:23 -0700 (PDT) Received: by mail-pj1-f53.google.com with SMTP id p4-20020a17090a9304b029016f3020d867so8302675pjo.3; Sun, 27 Jun 2021 01:23:22 -0700 (PDT) X-Received: by 2002:a17:90a:6be6:: with SMTP id w93mr20759803pjj.171.1624782202542; Sun, 27 Jun 2021 01:23:22 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-3-zhiwei_liu@c-sky.com> In-Reply-To: From: Frank Chang Date: Sun, 27 Jun 2021 16:23:10 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode To: Frank Chang Content-Type: multipart/alternative; boundary="000000000000051fd705c5bb162d" Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com, Palmer Dabbelt , Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000051fd705c5bb162d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Frank Chang =E6=96=BC 2021=E5=B9=B46=E6=9C=8827=E6= =97=A5 =E9=80=B1=E6=97=A5 =E4=B8=8A=E5=8D=881:23=E5=AF=AB=E9=81=93=EF=BC=9A > LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6= =97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:52=E5=AF=AB=E9=81=93=EF=BC=9A > >> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field >> for the threshold level of the associated privilege mode. >> >> For horizontal interrupts, only the ones with higher interrupt levels >> than the threshold level are allowed to preempt. >> >> Signed-off-by: LIU Zhiwei >> > > Reviewed-by: Frank Chang > Sorry, recall that mintthresh description is vague in v0.8 CLIC spec[1]. If mintthresh is a CLIC memory-mapped register in v0.8 CLIC. Then I think you should restrict the CSR accesses to mintthresh and sintthresh when CLIC is v0.8. [1] https://github.com/riscv/riscv-fast-interrupt/blob/74f86c3858/clic.adoc Regards, Frank Chang > > >> --- >> target/riscv/cpu.h | 2 ++ >> target/riscv/cpu_bits.h | 2 ++ >> target/riscv/csr.c | 28 ++++++++++++++++++++++++++++ >> 3 files changed, 32 insertions(+) >> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 1a44ca62c7..a5eab26a69 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -160,6 +160,7 @@ struct CPURISCVState { >> >> uint32_t miclaim; >> uint32_t mintstatus; /* clic-spec */ >> + target_ulong mintthresh; /* clic-spec */ >> >> target_ulong mie; >> target_ulong mideleg; >> @@ -173,6 +174,7 @@ struct CPURISCVState { >> target_ulong stvec; >> target_ulong sepc; >> target_ulong scause; >> + target_ulong sintthresh; /* clic-spec */ >> >> target_ulong mtvec; >> target_ulong mepc; >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index c4ce6ec3d9..9447801d22 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -166,6 +166,7 @@ >> #define CSR_MTVAL 0x343 >> #define CSR_MIP 0x344 >> #define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ >> +#define CSR_MINTTHRESH 0x347 /* clic-spec-draft */ >> >> /* Legacy Machine Trap Handling (priv v1.9.1) */ >> #define CSR_MBADADDR 0x343 >> @@ -185,6 +186,7 @@ >> #define CSR_STVAL 0x143 >> #define CSR_SIP 0x144 >> #define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ >> +#define CSR_SINTTHRESH 0x147 /* clic-spec-draft */ >> >> /* Legacy Supervisor Trap Handling (priv v1.9.1) */ >> #define CSR_SBADADDR 0x143 >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index 320b18ab60..4c31364967 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -746,6 +746,18 @@ static int read_mintstatus(CPURISCVState *env, int >> csrno, target_ulong *val) >> return 0; >> } >> >> +static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong >> *val) >> +{ >> + *val =3D env->mintthresh; >> + return 0; >> +} >> + >> +static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong >> val) >> +{ >> + env->mintthresh =3D val; >> + return 0; >> +} >> + >> /* Supervisor Trap Setup */ >> static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *va= l) >> { >> @@ -912,6 +924,18 @@ static int read_sintstatus(CPURISCVState *env, int >> csrno, target_ulong *val) >> return 0; >> } >> >> +static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong >> *val) >> +{ >> + *val =3D env->sintthresh; >> + return 0; >> +} >> + >> +static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong >> val) >> +{ >> + env->sintthresh =3D val; >> + return 0; >> +} >> + >> /* Supervisor Protection and Translation */ >> static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) >> { >> @@ -1666,9 +1690,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D = { >> >> /* Machine Mode Core Level Interrupt Controller */ >> [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, >> + [CSR_MINTTHRESH] =3D { "mintthresh", clic, read_mintthresh, >> + write_mintthresh }, >> >> /* Supervisor Mode Core Level Interrupt Controller */ >> [CSR_SINTSTATUS] =3D { "sintstatus", clic, read_sintstatus }, >> + [CSR_SINTTHRESH] =3D { "sintthresh", clic, read_sintthresh, >> + write_sintthresh }, >> >> #endif /* !CONFIG_USER_ONLY */ >> }; >> -- >> 2.25.1 >> >> >> --000000000000051fd705c5bb162d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Frank Chang <frank.chang@sifive.com> =E6=96=BC 2021=E5=B9=B46=E6= =9C=8827=E6=97=A5 =E9=80=B1=E6=97=A5 =E4=B8=8A=E5=8D=881:23=E5=AF=AB=E9=81= =93=EF=BC=9A
LIU Zhiwei <zhiwei_liu@c-sky.co= m> =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97=A5 =E9=80=B1=E4=BA=94 = =E4=B8=8B=E5=8D=883:52=E5=AF=AB=E9=81=93=EF=BC=9A
The interrupt-= level threshold (xintthresh) CSR holds an 8-bit field
for the threshold level of the associated privilege mode.

For horizontal interrupts, only the ones with higher interrupt levels
than the threshold level are allowed to preempt.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Reviewed-by: Frank Chang <frank.chang@sifive.com>

Sorry, recall that=C2=A0mintthresh description is va= gue in v0.8 CLIC spec[1].
If mintthresh is a CLIC memory-mapped r= egister in v0.8 CLIC.
Then I think you should restrict the CSR ac= cesses to mintthresh=C2=A0and sintthresh when CLIC is v0.8.

<= /div>

---
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/riscv/cpu_bits.h |=C2=A0 2 ++
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 28 +++++++++++++++++++++++++= +++
=C2=A03 files changed, 32 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1a44ca62c7..a5eab26a69 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -160,6 +160,7 @@ struct CPURISCVState {

=C2=A0 =C2=A0 =C2=A0uint32_t miclaim;
=C2=A0 =C2=A0 =C2=A0uint32_t mintstatus; /* clic-spec */
+=C2=A0 =C2=A0 target_ulong mintthresh; /* clic-spec */

=C2=A0 =C2=A0 =C2=A0target_ulong mie;
=C2=A0 =C2=A0 =C2=A0target_ulong mideleg;
@@ -173,6 +174,7 @@ struct CPURISCVState {
=C2=A0 =C2=A0 =C2=A0target_ulong stvec;
=C2=A0 =C2=A0 =C2=A0target_ulong sepc;
=C2=A0 =C2=A0 =C2=A0target_ulong scause;
+=C2=A0 =C2=A0 target_ulong sintthresh; /* clic-spec */

=C2=A0 =C2=A0 =C2=A0target_ulong mtvec;
=C2=A0 =C2=A0 =C2=A0target_ulong mepc;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index c4ce6ec3d9..9447801d22 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -166,6 +166,7 @@
=C2=A0#define CSR_MTVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x343
=C2=A0#define CSR_MIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x344<= br> =C2=A0#define CSR_MINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x346 /* clic-spec-draft *= /
+#define CSR_MINTTHRESH=C2=A0 =C2=A0 =C2=A0 0x347 /* clic-spec-draft */

=C2=A0/* Legacy Machine Trap Handling (priv v1.9.1) */
=C2=A0#define CSR_MBADADDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x343
@@ -185,6 +186,7 @@
=C2=A0#define CSR_STVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x143
=C2=A0#define CSR_SIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x144<= br> =C2=A0#define CSR_SINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x146 /* clic-spec-draft *= /
+#define CSR_SINTTHRESH=C2=A0 =C2=A0 =C2=A0 0x147 /* clic-spec-draft */

=C2=A0/* Legacy Supervisor Trap Handling (priv v1.9.1) */
=C2=A0#define CSR_SBADADDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x143
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 320b18ab60..4c31364967 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -746,6 +746,18 @@ static int read_mintstatus(CPURISCVState *env, int csr= no, target_ulong *val)
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}

+static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong *va= l)
+{
+=C2=A0 =C2=A0 *val =3D env->mintthresh;
+=C2=A0 =C2=A0 return 0;
+}
+
+static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong va= l)
+{
+=C2=A0 =C2=A0 env->mintthresh =3D val;
+=C2=A0 =C2=A0 return 0;
+}
+
=C2=A0/* Supervisor Trap Setup */
=C2=A0static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *= val)
=C2=A0{
@@ -912,6 +924,18 @@ static int read_sintstatus(CPURISCVState *env, int csr= no, target_ulong *val)
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}

+static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong *va= l)
+{
+=C2=A0 =C2=A0 *val =3D env->sintthresh;
+=C2=A0 =C2=A0 return 0;
+}
+
+static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong va= l)
+{
+=C2=A0 =C2=A0 env->sintthresh =3D val;
+=C2=A0 =C2=A0 return 0;
+}
+
=C2=A0/* Supervisor Protection and Translation */
=C2=A0static int read_satp(CPURISCVState *env, int csrno, target_ulong *val= )
=C2=A0{
@@ -1666,9 +1690,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {
=C2=A0 =C2=A0 =C2=A0/* Machine Mode Core Level Interrupt Controller */
=C2=A0 =C2=A0 =C2=A0[CSR_MINTSTATUS] =3D { "mintstatus", clic,=C2= =A0 read_mintstatus },
+=C2=A0 =C2=A0 [CSR_MINTTHRESH] =3D { "mintthresh", clic,=C2=A0 r= ead_mintthresh,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0write_mintthresh },

=C2=A0 =C2=A0 =C2=A0/* Supervisor Mode Core Level Interrupt Controller */ =C2=A0 =C2=A0 =C2=A0[CSR_SINTSTATUS] =3D { "sintstatus", clic,=C2= =A0 read_sintstatus },
+=C2=A0 =C2=A0 [CSR_SINTTHRESH] =3D { "sintthresh", clic,=C2=A0 r= ead_sintthresh,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0write_sintthresh },

=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
--
2.25.1


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[209.85.216.53]) by smtp.gmail.com with ESMTPSA id z27sm10872216pfg.91.2021.06.27.01.23.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Jun 2021 01:23:23 -0700 (PDT) Received: by mail-pj1-f53.google.com with SMTP id p4-20020a17090a9304b029016f3020d867so8302675pjo.3; Sun, 27 Jun 2021 01:23:22 -0700 (PDT) X-Received: by 2002:a17:90a:6be6:: with SMTP id w93mr20759803pjj.171.1624782202542; Sun, 27 Jun 2021 01:23:22 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-3-zhiwei_liu@c-sky.com> In-Reply-To: From: Frank Chang Date: Sun, 27 Jun 2021 16:23:10 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode To: Frank Chang Cc: LIU Zhiwei , "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , wxy194768@alibaba-inc.com Content-Type: multipart/alternative; boundary="000000000000051fd705c5bb162d" Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 27 Jun 2021 08:23:28 -0000 --000000000000051fd705c5bb162d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Frank Chang =E6=96=BC 2021=E5=B9=B46=E6=9C=8827=E6= =97=A5 =E9=80=B1=E6=97=A5 =E4=B8=8A=E5=8D=881:23=E5=AF=AB=E9=81=93=EF=BC=9A > LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6= =97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:52=E5=AF=AB=E9=81=93=EF=BC=9A > >> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field >> for the threshold level of the associated privilege mode. >> >> For horizontal interrupts, only the ones with higher interrupt levels >> than the threshold level are allowed to preempt. >> >> Signed-off-by: LIU Zhiwei >> > > Reviewed-by: Frank Chang > Sorry, recall that mintthresh description is vague in v0.8 CLIC spec[1]. If mintthresh is a CLIC memory-mapped register in v0.8 CLIC. Then I think you should restrict the CSR accesses to mintthresh and sintthresh when CLIC is v0.8. [1] https://github.com/riscv/riscv-fast-interrupt/blob/74f86c3858/clic.adoc Regards, Frank Chang > > >> --- >> target/riscv/cpu.h | 2 ++ >> target/riscv/cpu_bits.h | 2 ++ >> target/riscv/csr.c | 28 ++++++++++++++++++++++++++++ >> 3 files changed, 32 insertions(+) >> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 1a44ca62c7..a5eab26a69 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -160,6 +160,7 @@ struct CPURISCVState { >> >> uint32_t miclaim; >> uint32_t mintstatus; /* clic-spec */ >> + target_ulong mintthresh; /* clic-spec */ >> >> target_ulong mie; >> target_ulong mideleg; >> @@ -173,6 +174,7 @@ struct CPURISCVState { >> target_ulong stvec; >> target_ulong sepc; >> target_ulong scause; >> + target_ulong sintthresh; /* clic-spec */ >> >> target_ulong mtvec; >> target_ulong mepc; >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index c4ce6ec3d9..9447801d22 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -166,6 +166,7 @@ >> #define CSR_MTVAL 0x343 >> #define CSR_MIP 0x344 >> #define CSR_MINTSTATUS 0x346 /* clic-spec-draft */ >> +#define CSR_MINTTHRESH 0x347 /* clic-spec-draft */ >> >> /* Legacy Machine Trap Handling (priv v1.9.1) */ >> #define CSR_MBADADDR 0x343 >> @@ -185,6 +186,7 @@ >> #define CSR_STVAL 0x143 >> #define CSR_SIP 0x144 >> #define CSR_SINTSTATUS 0x146 /* clic-spec-draft */ >> +#define CSR_SINTTHRESH 0x147 /* clic-spec-draft */ >> >> /* Legacy Supervisor Trap Handling (priv v1.9.1) */ >> #define CSR_SBADADDR 0x143 >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index 320b18ab60..4c31364967 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -746,6 +746,18 @@ static int read_mintstatus(CPURISCVState *env, int >> csrno, target_ulong *val) >> return 0; >> } >> >> +static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong >> *val) >> +{ >> + *val =3D env->mintthresh; >> + return 0; >> +} >> + >> +static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong >> val) >> +{ >> + env->mintthresh =3D val; >> + return 0; >> +} >> + >> /* Supervisor Trap Setup */ >> static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *va= l) >> { >> @@ -912,6 +924,18 @@ static int read_sintstatus(CPURISCVState *env, int >> csrno, target_ulong *val) >> return 0; >> } >> >> +static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong >> *val) >> +{ >> + *val =3D env->sintthresh; >> + return 0; >> +} >> + >> +static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong >> val) >> +{ >> + env->sintthresh =3D val; >> + return 0; >> +} >> + >> /* Supervisor Protection and Translation */ >> static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) >> { >> @@ -1666,9 +1690,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D = { >> >> /* Machine Mode Core Level Interrupt Controller */ >> [CSR_MINTSTATUS] =3D { "mintstatus", clic, read_mintstatus }, >> + [CSR_MINTTHRESH] =3D { "mintthresh", clic, read_mintthresh, >> + write_mintthresh }, >> >> /* Supervisor Mode Core Level Interrupt Controller */ >> [CSR_SINTSTATUS] =3D { "sintstatus", clic, read_sintstatus }, >> + [CSR_SINTTHRESH] =3D { "sintthresh", clic, read_sintthresh, >> + write_sintthresh }, >> >> #endif /* !CONFIG_USER_ONLY */ >> }; >> -- >> 2.25.1 >> >> >> --000000000000051fd705c5bb162d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Frank Chang <frank.chang@sifive.com> =E6=96=BC 2021=E5=B9=B46=E6= =9C=8827=E6=97=A5 =E9=80=B1=E6=97=A5 =E4=B8=8A=E5=8D=881:23=E5=AF=AB=E9=81= =93=EF=BC=9A
LIU Zhiwei <zhiwei_liu@c-sky.co= m> =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97=A5 =E9=80=B1=E4=BA=94 = =E4=B8=8B=E5=8D=883:52=E5=AF=AB=E9=81=93=EF=BC=9A
The interrupt-= level threshold (xintthresh) CSR holds an 8-bit field
for the threshold level of the associated privilege mode.

For horizontal interrupts, only the ones with higher interrupt levels
than the threshold level are allowed to preempt.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Reviewed-by: Frank Chang <frank.chang@sifive.com>

Sorry, recall that=C2=A0mintthresh description is va= gue in v0.8 CLIC spec[1].
If mintthresh is a CLIC memory-mapped r= egister in v0.8 CLIC.
Then I think you should restrict the CSR ac= cesses to mintthresh=C2=A0and sintthresh when CLIC is v0.8.

<= /div>

---
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 2 ++
=C2=A0target/riscv/cpu_bits.h |=C2=A0 2 ++
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 28 +++++++++++++++++++++++++= +++
=C2=A03 files changed, 32 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1a44ca62c7..a5eab26a69 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -160,6 +160,7 @@ struct CPURISCVState {

=C2=A0 =C2=A0 =C2=A0uint32_t miclaim;
=C2=A0 =C2=A0 =C2=A0uint32_t mintstatus; /* clic-spec */
+=C2=A0 =C2=A0 target_ulong mintthresh; /* clic-spec */

=C2=A0 =C2=A0 =C2=A0target_ulong mie;
=C2=A0 =C2=A0 =C2=A0target_ulong mideleg;
@@ -173,6 +174,7 @@ struct CPURISCVState {
=C2=A0 =C2=A0 =C2=A0target_ulong stvec;
=C2=A0 =C2=A0 =C2=A0target_ulong sepc;
=C2=A0 =C2=A0 =C2=A0target_ulong scause;
+=C2=A0 =C2=A0 target_ulong sintthresh; /* clic-spec */

=C2=A0 =C2=A0 =C2=A0target_ulong mtvec;
=C2=A0 =C2=A0 =C2=A0target_ulong mepc;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index c4ce6ec3d9..9447801d22 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -166,6 +166,7 @@
=C2=A0#define CSR_MTVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x343
=C2=A0#define CSR_MIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x344<= br> =C2=A0#define CSR_MINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x346 /* clic-spec-draft *= /
+#define CSR_MINTTHRESH=C2=A0 =C2=A0 =C2=A0 0x347 /* clic-spec-draft */

=C2=A0/* Legacy Machine Trap Handling (priv v1.9.1) */
=C2=A0#define CSR_MBADADDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x343
@@ -185,6 +186,7 @@
=C2=A0#define CSR_STVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x143
=C2=A0#define CSR_SIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x144<= br> =C2=A0#define CSR_SINTSTATUS=C2=A0 =C2=A0 =C2=A0 0x146 /* clic-spec-draft *= /
+#define CSR_SINTTHRESH=C2=A0 =C2=A0 =C2=A0 0x147 /* clic-spec-draft */

=C2=A0/* Legacy Supervisor Trap Handling (priv v1.9.1) */
=C2=A0#define CSR_SBADADDR=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x143
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 320b18ab60..4c31364967 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -746,6 +746,18 @@ static int read_mintstatus(CPURISCVState *env, int csr= no, target_ulong *val)
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}

+static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong *va= l)
+{
+=C2=A0 =C2=A0 *val =3D env->mintthresh;
+=C2=A0 =C2=A0 return 0;
+}
+
+static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong va= l)
+{
+=C2=A0 =C2=A0 env->mintthresh =3D val;
+=C2=A0 =C2=A0 return 0;
+}
+
=C2=A0/* Supervisor Trap Setup */
=C2=A0static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *= val)
=C2=A0{
@@ -912,6 +924,18 @@ static int read_sintstatus(CPURISCVState *env, int csr= no, target_ulong *val)
=C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0}

+static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong *va= l)
+{
+=C2=A0 =C2=A0 *val =3D env->sintthresh;
+=C2=A0 =C2=A0 return 0;
+}
+
+static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong va= l)
+{
+=C2=A0 =C2=A0 env->sintthresh =3D val;
+=C2=A0 =C2=A0 return 0;
+}
+
=C2=A0/* Supervisor Protection and Translation */
=C2=A0static int read_satp(CPURISCVState *env, int csrno, target_ulong *val= )
=C2=A0{
@@ -1666,9 +1690,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {
=C2=A0 =C2=A0 =C2=A0/* Machine Mode Core Level Interrupt Controller */
=C2=A0 =C2=A0 =C2=A0[CSR_MINTSTATUS] =3D { "mintstatus", clic,=C2= =A0 read_mintstatus },
+=C2=A0 =C2=A0 [CSR_MINTTHRESH] =3D { "mintthresh", clic,=C2=A0 r= ead_mintthresh,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0write_mintthresh },

=C2=A0 =C2=A0 =C2=A0/* Supervisor Mode Core Level Interrupt Controller */ =C2=A0 =C2=A0 =C2=A0[CSR_SINTSTATUS] =3D { "sintstatus", clic,=C2= =A0 read_sintstatus },
+=C2=A0 =C2=A0 [CSR_SINTTHRESH] =3D { "sintthresh", clic,=C2=A0 r= ead_sintthresh,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0write_sintthresh },

=C2=A0#endif /* !CONFIG_USER_ONLY */
=C2=A0};
--
2.25.1


--000000000000051fd705c5bb162d--