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* [RFC PATCH 00/11] RISC-V: support clic v0.9 specification
@ 2021-04-09  7:48 ` LIU Zhiwei
  0 siblings, 0 replies; 162+ messages in thread
From: LIU Zhiwei @ 2021-04-09  7:48 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv; +Cc: palmer, Alistair.Francis, LIU Zhiwei, wxy194768

This patch set gives an implementation of "RISC-V Core-Local Interrupt
Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
you can find the pdf format or the source code.

I take over the job from Michael Clark, who gave the first implementation
of clic-v0.7 specification. If there is any copyright question, please
let me know.

Features:
1. support four kinds of trigger types.
2. Preserve the CSR WARL/WPRI semantics. 
3. Option to select different modes, such as M/S/U or M/U.
4. At most 4096 interrupts.
5. At most 1024 apertures.

Todo:
1. Encode the interrupt trigger information to exccode.
2. Support complete CSR mclicbase when its number is fixed. 
3. Gave each aperture an independend address.

It have passed my qtest case and freertos test. Welcome to have a try
for your hardware.

Any advice is welcomed. Thanks very much.

Zhiwei

[1] specification website: https://github.com/riscv/riscv-fast-interrupt.
[2] Michael Clark origin work: https://github.com/sifive/riscv-qemu/tree/sifive-clic.


LIU Zhiwei (11):
  target/riscv: Add CLIC CSR mintstatus
  target/riscv: Update CSR xintthresh in CLIC mode
  hw/intc: Add CLIC device
  target/riscv: Update CSR xie in CLIC mode
  target/riscv: Update CSR xip in CLIC mode
  target/riscv: Update CSR xtvec in CLIC mode
  target/riscv: Update CSR xtvt in CLIC mode
  target/riscv: Update CSR xnxti in CLIC mode
  target/riscv: Update CSR mclicbase in CLIC mode
  target/riscv: Update interrupt handling in CLIC mode
  target/riscv: Update interrupt return in CLIC mode

 default-configs/devices/riscv32-softmmu.mak |   1 +
 default-configs/devices/riscv64-softmmu.mak |   1 +
 hw/intc/Kconfig                             |   3 +
 hw/intc/meson.build                         |   1 +
 hw/intc/riscv_clic.c                        | 836 ++++++++++++++++++++
 include/hw/intc/riscv_clic.h                | 103 +++
 target/riscv/cpu.h                          |   9 +
 target/riscv/cpu_bits.h                     |  32 +
 target/riscv/cpu_helper.c                   | 117 ++-
 target/riscv/csr.c                          | 247 +++++-
 target/riscv/op_helper.c                    |  25 +
 11 files changed, 1363 insertions(+), 12 deletions(-)
 create mode 100644 hw/intc/riscv_clic.c
 create mode 100644 include/hw/intc/riscv_clic.h

-- 
2.25.1



^ permalink raw reply	[flat|nested] 162+ messages in thread

end of thread, other threads:[~2021-09-29  3:57 UTC | newest]

Thread overview: 162+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-09  7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei
2021-04-09  7:48 ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:23   ` Alistair Francis
2021-04-19 23:23     ` Alistair Francis
2021-04-20  0:49     ` LIU Zhiwei
2021-04-20  0:49       ` LIU Zhiwei
2021-07-01  8:45       ` Frank Chang
2021-07-01  8:45         ` Frank Chang
2021-07-01  9:38         ` LIU Zhiwei
2021-07-01  9:38           ` LIU Zhiwei
2021-07-02  5:38         ` Alistair Francis
2021-07-02  5:38           ` Alistair Francis
2021-07-02  6:09           ` LIU Zhiwei
2021-07-02  6:09             ` LIU Zhiwei
2021-07-02  7:16             ` Alistair Francis
2021-07-02  7:16               ` Alistair Francis
2021-09-28  8:10               ` Frank Chang
2021-09-28  8:10                 ` Frank Chang
2021-09-29  3:55                 ` Alistair Francis
2021-09-29  3:55                   ` Alistair Francis
2021-04-09  7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 17:23   ` Frank Chang
2021-06-26 17:23     ` Frank Chang
2021-06-27  8:23     ` Frank Chang
2021-06-27  8:23       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:25   ` Alistair Francis
2021-04-19 23:25     ` Alistair Francis
2021-04-20  0:57     ` LIU Zhiwei
2021-04-20  0:57       ` LIU Zhiwei
2021-04-22  0:16       ` Alistair Francis
2021-04-22  0:16         ` Alistair Francis
2021-06-13 10:10   ` Frank Chang
2021-06-13 10:10     ` Frank Chang
2021-06-16  2:56     ` LIU Zhiwei
2021-06-16  2:56       ` LIU Zhiwei
2021-06-26 12:56       ` Frank Chang
2021-06-26 12:56         ` Frank Chang
2021-06-28  7:15         ` LIU Zhiwei
2021-06-28  7:15           ` LIU Zhiwei
2021-06-28  7:23           ` Frank Chang
2021-06-28  7:23             ` Frank Chang
2021-06-28  7:39             ` LIU Zhiwei
2021-06-28  7:39               ` LIU Zhiwei
2021-06-28  7:49               ` Frank Chang
2021-06-28  7:49                 ` Frank Chang
2021-06-28  8:01                 ` LIU Zhiwei
2021-06-28  8:01                   ` LIU Zhiwei
2021-06-28  8:07                   ` Frank Chang
2021-06-28  8:07                     ` Frank Chang
2021-06-28  8:11                     ` LIU Zhiwei
2021-06-28  8:11                       ` LIU Zhiwei
2021-06-28  8:19                       ` Frank Chang
2021-06-28  8:19                         ` Frank Chang
2021-06-28  8:43                         ` LIU Zhiwei
2021-06-28  8:43                           ` LIU Zhiwei
2021-06-28  9:11                           ` Frank Chang
2021-06-28  9:11                             ` Frank Chang
2021-06-26 15:03   ` Frank Chang
2021-06-26 15:03     ` Frank Chang
2021-06-26 15:26     ` Frank Chang
2021-06-26 15:26       ` Frank Chang
2021-06-29  2:52       ` LIU Zhiwei
2021-06-29  2:52         ` LIU Zhiwei
2021-06-29  2:43     ` LIU Zhiwei
2021-06-29  2:43       ` LIU Zhiwei
2021-06-30  5:37       ` Frank Chang
2021-06-30  5:37         ` Frank Chang
2021-06-26 15:20   ` Frank Chang
2021-06-26 15:20     ` Frank Chang
2021-06-29  2:50     ` LIU Zhiwei
2021-06-29  2:50       ` LIU Zhiwei
2021-06-26 17:15   ` Frank Chang
2021-06-26 17:15     ` Frank Chang
2021-06-26 17:19     ` Frank Chang
2021-06-26 17:19       ` Frank Chang
2021-06-28 10:16   ` Frank Chang
2021-06-28 10:16     ` Frank Chang
2021-06-28 12:56     ` LIU Zhiwei
2021-06-28 12:56       ` LIU Zhiwei
2021-06-28 14:30       ` Frank Chang
2021-06-28 14:30         ` Frank Chang
2021-06-28 21:36         ` LIU Zhiwei
2021-06-28 21:36           ` LIU Zhiwei
2021-06-28 10:24   ` Frank Chang
2021-06-28 10:24     ` Frank Chang
2021-06-28 10:48     ` LIU Zhiwei
2021-06-28 10:48       ` LIU Zhiwei
2021-07-13  6:53   ` Frank Chang
2021-07-13  6:53     ` Frank Chang
2021-07-13  6:57     ` Frank Chang
2021-07-13  6:57       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:50   ` Frank Chang
2021-06-27  6:50     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:45   ` Frank Chang
2021-06-27  6:45     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  8:59   ` Frank Chang
2021-06-27  8:59     ` Frank Chang
2021-07-10 15:04   ` Frank Chang
2021-07-10 15:04     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  8:33   ` Frank Chang
2021-06-27  8:33     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-11  8:15   ` Frank Chang
2021-06-11  8:15     ` Frank Chang
2021-06-11  8:30     ` LIU Zhiwei
2021-06-11  8:30       ` LIU Zhiwei
2021-06-11  8:42       ` Frank Chang
2021-06-11  8:42         ` Frank Chang
2021-06-11  8:56         ` LIU Zhiwei
2021-06-11  8:56           ` LIU Zhiwei
2021-06-11  9:07           ` Frank Chang
2021-06-11  9:07             ` Frank Chang
2021-06-11  9:26             ` LIU Zhiwei
2021-06-11  9:26               ` LIU Zhiwei
2021-06-15  7:45             ` Alistair Francis
2021-06-15  7:45               ` Alistair Francis
2021-06-27 10:07   ` Frank Chang
2021-06-27 10:07     ` Frank Chang
2021-07-10 14:59   ` Frank Chang
2021-07-10 14:59     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 15:31   ` Frank Chang
2021-06-26 15:31     ` Frank Chang
2021-06-29  2:54     ` LIU Zhiwei
2021-06-29  2:54       ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27 15:39   ` Frank Chang
2021-06-27 15:39     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27 12:08   ` Frank Chang
2021-06-27 12:08     ` Frank Chang
2021-07-13  7:15   ` Frank Chang
2021-07-13  7:15     ` Frank Chang
2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis
2021-04-19 23:30   ` Alistair Francis
2021-04-20  1:44   ` LIU Zhiwei
2021-04-20  1:44     ` LIU Zhiwei
2021-04-20  6:26     ` Alistair Francis
2021-04-20  6:26       ` Alistair Francis
2021-04-20  7:20       ` LIU Zhiwei
2021-04-20  7:20         ` LIU Zhiwei
2021-04-22  0:21         ` Alistair Francis
2021-04-22  0:21           ` Alistair Francis
2021-06-27 15:55 ` Frank Chang
2021-06-27 15:55   ` Frank Chang

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