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[209.85.210.171]) by smtp.gmail.com with ESMTPSA id b33sm11232098pgb.92.2021.07.10.08.04.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Jul 2021 08:04:55 -0700 (PDT) Received: by mail-pf1-f171.google.com with SMTP id b12so11634580pfv.6; Sat, 10 Jul 2021 08:04:55 -0700 (PDT) X-Received: by 2002:a63:655:: with SMTP id 82mr12467700pgg.133.1625929495457; Sat, 10 Jul 2021 08:04:55 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-7-zhiwei_liu@c-sky.com> In-Reply-To: <20210409074857.166082-7-zhiwei_liu@c-sky.com> From: Frank Chang Date: Sat, 10 Jul 2021 23:04:44 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode To: LIU Zhiwei Content-Type: multipart/alternative; boundary="00000000000001b38205c6c636d1" Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --00000000000001b38205c6c636d1 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:51=E5=AF=AB=E9=81=93=EF=BC=9A > The new CLIC interrupt-handling mode is encoded as a new state in the > existing WARL xtvec register, where the low two bits of are 11. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index f6c84b9fe4..39ff72041a 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno, > target_ulong *val) > > static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) > { > - /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D rese= rved */ > + /* > + * bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 3 =3D CLIC, > + * others reserved > + */ > if ((val & 3) < 2) { > env->mtvec =3D val; > We might need to zero new fields in mcause when set back to basic mode: Section 4.7: When basic mode is written to xtvec, the new xcause state fields (mhinv and mpil) are zeroed. The other new xcause fields, mpp and mpie, appear as zero in the xcause CSR but the corresponding state bits in the mstatus register are not cleared. > + } else if ((val & 1) && env->clic) { > + /* > + * If only CLIC mode is supported, writes to bit 1 are also > ignored and > + * it is always set to one. CLIC mode hardwires xtvec bits 2-5 t= o > zero. > + */ > + env->mtvec =3D ((val & ~0x3f) << 6) | (0b000011); > } else { > qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not > supported\n"); > } > @@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno, > target_ulong *val) > > static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) > { > - /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D rese= rved */ > + /* > + * bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 3 =3D CLIC, > + * others reserved > + */ > if ((val & 3) < 2) { > env->stvec =3D val; > Same to write_mtvec() Regards, Frank Chang > + } else if ((val & 1) && env->clic) { > + /* > + * If only CLIC mode is supported, writes to bit 1 are also > ignored and > + * it is always set to one. CLIC mode hardwires xtvec bits 2-5 t= o > zero. > + */ > + env->stvec =3D ((val & ~0x3f) << 6) | (0b000011); > } else { > qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not > supported\n"); > } > -- > 2.25.1 > > > --00000000000001b38205c6c636d1 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C= =889=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:51=E5=AF=AB=E9=81=93= =EF=BC=9A
The new CLIC interrupt-handling mode is encoded as a n= ew state in the
existing WARL xtvec register, where the low two bits of are 11.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
=C2=A0target/riscv/csr.c | 22 ++++++++++++++++++++--
=C2=A01 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f6c84b9fe4..39ff72041a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno, t= arget_ulong *val)

=C2=A0static int write_mtvec(CPURISCVState *env, int csrno, target_ulong va= l)
=C2=A0{
-=C2=A0 =C2=A0 /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 &= gt;=3D reserved */
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored= , 3 =3D CLIC,
+=C2=A0 =C2=A0 =C2=A0* others reserved
+=C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0if ((val & 3) < 2) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->mtvec =3D val;

We might need to zero new fields in mcause when set back = to basic mode:

Section 4.7:
When basic m= ode is written to xtvec,
the new xcause state fields (mhinv and m= pil) are zeroed.
The other new xcause fields, mpp and mpie, appea= r as zero in the xcause CSR
but the corresponding state bits in t= he mstatus register are not cleared.
=C2=A0
+=C2=A0 =C2=A0 } else if ((val & 1) && env->clic) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* If only CLIC mode is supported, writes= to bit 1 are also ignored and
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* it is always set to one. CLIC mode har= dwires xtvec bits 2-5 to zero.
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mtvec =3D ((val & ~0x3f) << = 6) | (0b000011);
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_log_mask(LOG_UNIMP, "CSR_MTVEC:= reserved mode not supported\n");
=C2=A0 =C2=A0 =C2=A0}
@@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno, t= arget_ulong *val)

=C2=A0static int write_stvec(CPURISCVState *env, int csrno, target_ulong va= l)
=C2=A0{
-=C2=A0 =C2=A0 /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 &= gt;=3D reserved */
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored= , 3 =3D CLIC,
+=C2=A0 =C2=A0 =C2=A0* others reserved
+=C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0if ((val & 3) < 2) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->stvec =3D val;

Same to write_mtvec()

Regards,
Frank Chang
=C2=A0
+=C2=A0 =C2=A0 } else if ((val & 1) && env->clic) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* If only CLIC mode is supported, writes= to bit 1 are also ignored and
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* it is always set to one. CLIC mode har= dwires xtvec bits 2-5 to zero.
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->stvec =3D ((val & ~0x3f) << = 6) | (0b000011);
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_log_mask(LOG_UNIMP, "CSR_STVEC:= reserved mode not supported\n");
=C2=A0 =C2=A0 =C2=A0}
--
2.25.1


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[209.85.210.171]) by smtp.gmail.com with ESMTPSA id b33sm11232098pgb.92.2021.07.10.08.04.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Jul 2021 08:04:55 -0700 (PDT) Received: by mail-pf1-f171.google.com with SMTP id b12so11634580pfv.6; Sat, 10 Jul 2021 08:04:55 -0700 (PDT) X-Received: by 2002:a63:655:: with SMTP id 82mr12467700pgg.133.1625929495457; Sat, 10 Jul 2021 08:04:55 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-7-zhiwei_liu@c-sky.com> In-Reply-To: <20210409074857.166082-7-zhiwei_liu@c-sky.com> From: Frank Chang Date: Sat, 10 Jul 2021 23:04:44 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode To: LIU Zhiwei Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , wxy194768@alibaba-inc.com Content-Type: multipart/alternative; boundary="00000000000001b38205c6c636d1" Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 10 Jul 2021 15:05:00 -0000 --00000000000001b38205c6c636d1 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:51=E5=AF=AB=E9=81=93=EF=BC=9A > The new CLIC interrupt-handling mode is encoded as a new state in the > existing WARL xtvec register, where the low two bits of are 11. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/csr.c | 22 ++++++++++++++++++++-- > 1 file changed, 20 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index f6c84b9fe4..39ff72041a 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno, > target_ulong *val) > > static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) > { > - /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D rese= rved */ > + /* > + * bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 3 =3D CLIC, > + * others reserved > + */ > if ((val & 3) < 2) { > env->mtvec =3D val; > We might need to zero new fields in mcause when set back to basic mode: Section 4.7: When basic mode is written to xtvec, the new xcause state fields (mhinv and mpil) are zeroed. The other new xcause fields, mpp and mpie, appear as zero in the xcause CSR but the corresponding state bits in the mstatus register are not cleared. > + } else if ((val & 1) && env->clic) { > + /* > + * If only CLIC mode is supported, writes to bit 1 are also > ignored and > + * it is always set to one. CLIC mode hardwires xtvec bits 2-5 t= o > zero. > + */ > + env->mtvec =3D ((val & ~0x3f) << 6) | (0b000011); > } else { > qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not > supported\n"); > } > @@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno, > target_ulong *val) > > static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) > { > - /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 >=3D rese= rved */ > + /* > + * bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 3 =3D CLIC, > + * others reserved > + */ > if ((val & 3) < 2) { > env->stvec =3D val; > Same to write_mtvec() Regards, Frank Chang > + } else if ((val & 1) && env->clic) { > + /* > + * If only CLIC mode is supported, writes to bit 1 are also > ignored and > + * it is always set to one. CLIC mode hardwires xtvec bits 2-5 t= o > zero. > + */ > + env->stvec =3D ((val & ~0x3f) << 6) | (0b000011); > } else { > qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not > supported\n"); > } > -- > 2.25.1 > > > --00000000000001b38205c6c636d1 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C= =889=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:51=E5=AF=AB=E9=81=93= =EF=BC=9A
The new CLIC interrupt-handling mode is encoded as a n= ew state in the
existing WARL xtvec register, where the low two bits of are 11.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
=C2=A0target/riscv/csr.c | 22 ++++++++++++++++++++--
=C2=A01 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f6c84b9fe4..39ff72041a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno, t= arget_ulong *val)

=C2=A0static int write_mtvec(CPURISCVState *env, int csrno, target_ulong va= l)
=C2=A0{
-=C2=A0 =C2=A0 /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 &= gt;=3D reserved */
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored= , 3 =3D CLIC,
+=C2=A0 =C2=A0 =C2=A0* others reserved
+=C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0if ((val & 3) < 2) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->mtvec =3D val;

We might need to zero new fields in mcause when set back = to basic mode:

Section 4.7:
When basic m= ode is written to xtvec,
the new xcause state fields (mhinv and m= pil) are zeroed.
The other new xcause fields, mpp and mpie, appea= r as zero in the xcause CSR
but the corresponding state bits in t= he mstatus register are not cleared.
=C2=A0
+=C2=A0 =C2=A0 } else if ((val & 1) && env->clic) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* If only CLIC mode is supported, writes= to bit 1 are also ignored and
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* it is always set to one. CLIC mode har= dwires xtvec bits 2-5 to zero.
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mtvec =3D ((val & ~0x3f) << = 6) | (0b000011);
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_log_mask(LOG_UNIMP, "CSR_MTVEC:= reserved mode not supported\n");
=C2=A0 =C2=A0 =C2=A0}
@@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno, t= arget_ulong *val)

=C2=A0static int write_stvec(CPURISCVState *env, int csrno, target_ulong va= l)
=C2=A0{
-=C2=A0 =C2=A0 /* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored, 2 &= gt;=3D reserved */
+=C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0* bits [1:0] encode mode; 0 =3D direct, 1 =3D vectored= , 3 =3D CLIC,
+=C2=A0 =C2=A0 =C2=A0* others reserved
+=C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0if ((val & 3) < 2) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->stvec =3D val;

Same to write_mtvec()

Regards,
Frank Chang
=C2=A0
+=C2=A0 =C2=A0 } else if ((val & 1) && env->clic) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* If only CLIC mode is supported, writes= to bit 1 are also ignored and
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* it is always set to one. CLIC mode har= dwires xtvec bits 2-5 to zero.
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->stvec =3D ((val & ~0x3f) << = 6) | (0b000011);
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_log_mask(LOG_UNIMP, "CSR_STVEC:= reserved mode not supported\n");
=C2=A0 =C2=A0 =C2=A0}
--
2.25.1


--00000000000001b38205c6c636d1--