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[209.85.214.169]) by smtp.gmail.com with ESMTPSA id m1sm17772884pjk.35.2021.06.27.08.55.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Jun 2021 08:55:46 -0700 (PDT) Received: by mail-pl1-f169.google.com with SMTP id h1so7478676plt.1; Sun, 27 Jun 2021 08:55:46 -0700 (PDT) X-Received: by 2002:a17:90a:6be6:: with SMTP id w93mr22509260pjj.171.1624809346006; Sun, 27 Jun 2021 08:55:46 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> From: Frank Chang Date: Sun, 27 Jun 2021 23:55:35 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification To: LIU Zhiwei Content-Type: multipart/alternative; boundary="000000000000e5853905c5c1670d" Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000e5853905c5c1670d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:58=E5=AF=AB=E9=81=93=EF=BC=9A > This patch set gives an implementation of "RISC-V Core-Local Interrupt > Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where > you can find the pdf format or the source code. > > I take over the job from Michael Clark, who gave the first implementation > of clic-v0.7 specification. If there is any copyright question, please > let me know. > > Features: > 1. support four kinds of trigger types. > 2. Preserve the CSR WARL/WPRI semantics. > 3. Option to select different modes, such as M/S/U or M/U. > 4. At most 4096 interrupts. > 5. At most 1024 apertures. > > Todo: > 1. Encode the interrupt trigger information to exccode. > 2. Support complete CSR mclicbase when its number is fixed. > 3. Gave each aperture an independend address. > > It have passed my qtest case and freertos test. Welcome to have a try > for your hardware. > > Any advice is welcomed. Thanks very much. > > Zhiwei > > [1] specification website: https://github.com/riscv/riscv-fast-interrupt. > [2] Michael Clark origin work: > https://github.com/sifive/riscv-qemu/tree/sifive-clic. > > > LIU Zhiwei (11): > target/riscv: Add CLIC CSR mintstatus > target/riscv: Update CSR xintthresh in CLIC mode > hw/intc: Add CLIC device > target/riscv: Update CSR xie in CLIC mode > target/riscv: Update CSR xip in CLIC mode > target/riscv: Update CSR xtvec in CLIC mode > target/riscv: Update CSR xtvt in CLIC mode > target/riscv: Update CSR xnxti in CLIC mode > target/riscv: Update CSR mclicbase in CLIC mode > target/riscv: Update interrupt handling in CLIC mode > target/riscv: Update interrupt return in CLIC mode > > default-configs/devices/riscv32-softmmu.mak | 1 + > default-configs/devices/riscv64-softmmu.mak | 1 + > hw/intc/Kconfig | 3 + > hw/intc/meson.build | 1 + > hw/intc/riscv_clic.c | 836 ++++++++++++++++++++ > include/hw/intc/riscv_clic.h | 103 +++ > target/riscv/cpu.h | 9 + > target/riscv/cpu_bits.h | 32 + > target/riscv/cpu_helper.c | 117 ++- > target/riscv/csr.c | 247 +++++- > target/riscv/op_helper.c | 25 + > 11 files changed, 1363 insertions(+), 12 deletions(-) > create mode 100644 hw/intc/riscv_clic.c > create mode 100644 include/hw/intc/riscv_clic.h > > -- > 2.25.1 > > > After reviewing this patchset. I found that CLIC v0.8 spec is quite incomplete. It lacks all S-mode related CSRs. If you think that it's just the v0.8 spec issue for not covering all the required S-mode related CSRs -- and we should include them in CLIC v0.8 implementation even it's not documented explicitly. You can just ignore my comments in regard to S-mode CSRs for v0.8 CLIC. (Besides mintthresh, v0.8 spec does say that it holds the 8-bit field interrupt thresholds for each privilege mode.) Regards, Frank Chang --000000000000e5853905c5c1670d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C= =889=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:58=E5=AF=AB=E9=81=93= =EF=BC=9A
This patch set gives an implementation of "RISC-V= Core-Local Interrupt
Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where=
you can find the pdf format or the source code.

I take over the job from Michael Clark, who gave the first implementation of clic-v0.7 specification. If there is any copyright question, please
let me know.

Features:
1. support four kinds of trigger types.
2. Preserve the CSR WARL/WPRI semantics.
3. Option to select different modes, such as M/S/U or M/U.
4. At most 4096 interrupts.
5. At most 1024 apertures.

Todo:
1. Encode the interrupt trigger information to exccode.
2. Support complete CSR mclicbase when its number is fixed.
3. Gave each aperture an independend address.

It have passed my qtest case and freertos test. Welcome to have a try
for your hardware.

Any advice is welcomed. Thanks very much.

Zhiwei

[1] specification website: https://github.com/riscv/ris= cv-fast-interrupt.
[2] Michael Clark origin work: https://github.c= om/sifive/riscv-qemu/tree/sifive-clic.


LIU Zhiwei (11):
=C2=A0 target/riscv: Add CLIC CSR mintstatus
=C2=A0 target/riscv: Update CSR xintthresh in CLIC mode
=C2=A0 hw/intc: Add CLIC device
=C2=A0 target/riscv: Update CSR xie in CLIC mode
=C2=A0 target/riscv: Update CSR xip in CLIC mode
=C2=A0 target/riscv: Update CSR xtvec in CLIC mode
=C2=A0 target/riscv: Update CSR xtvt in CLIC mode
=C2=A0 target/riscv: Update CSR xnxti in CLIC mode
=C2=A0 target/riscv: Update CSR mclicbase in CLIC mode
=C2=A0 target/riscv: Update interrupt handling in CLIC mode
=C2=A0 target/riscv: Update interrupt return in CLIC mode

=C2=A0default-configs/devices/riscv32-softmmu.mak |=C2=A0 =C2=A01 +
=C2=A0default-configs/devices/riscv64-softmmu.mak |=C2=A0 =C2=A01 +
=C2=A0hw/intc/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A03 +
=C2=A0hw/intc/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
=C2=A0hw/intc/riscv_clic.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 836 ++++++++++++++++++++
=C2=A0include/hw/intc/riscv_clic.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 | 103 +++
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A09 +
=C2=A0target/riscv/cpu_bits.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 32 +
=C2=A0target/riscv/cpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0| 117 ++-
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 247 +++++-
=C2=A0target/riscv/op_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 25 +
=C2=A011 files changed, 1363 insertions(+), 12 deletions(-)
=C2=A0create mode 100644 hw/intc/riscv_clic.c
=C2=A0create mode 100644 include/hw/intc/riscv_clic.h

--
2.25.1



After reviewing this patchset.
I found that CLIC v0.8 spec is quite incomplete.
It lacks all = S-mode related CSRs.

If you think that it'= s just the v0.8 spec issue for not covering
all the required S-mo= de related CSRs -- and we should include them
in CLIC v0.8 implem= entation even it's not documented explicitly.
You can just ig= nore my comments in regard to S-mode CSRs for v0.8 CLIC.
(Besides= =C2=A0mintthresh, v0.8 spec does say that it holds the 8-bit field
interrupt thresholds for each privilege mode.)

R= egards,
Frank Chang
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[209.85.214.169]) by smtp.gmail.com with ESMTPSA id m1sm17772884pjk.35.2021.06.27.08.55.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Jun 2021 08:55:46 -0700 (PDT) Received: by mail-pl1-f169.google.com with SMTP id h1so7478676plt.1; Sun, 27 Jun 2021 08:55:46 -0700 (PDT) X-Received: by 2002:a17:90a:6be6:: with SMTP id w93mr22509260pjj.171.1624809346006; Sun, 27 Jun 2021 08:55:46 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com> From: Frank Chang Date: Sun, 27 Jun 2021 23:55:35 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification To: LIU Zhiwei Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , wxy194768@alibaba-inc.com Content-Type: multipart/alternative; boundary="000000000000e5853905c5c1670d" Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 27 Jun 2021 15:55:54 -0000 --000000000000e5853905c5c1670d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:58=E5=AF=AB=E9=81=93=EF=BC=9A > This patch set gives an implementation of "RISC-V Core-Local Interrupt > Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where > you can find the pdf format or the source code. > > I take over the job from Michael Clark, who gave the first implementation > of clic-v0.7 specification. If there is any copyright question, please > let me know. > > Features: > 1. support four kinds of trigger types. > 2. Preserve the CSR WARL/WPRI semantics. > 3. Option to select different modes, such as M/S/U or M/U. > 4. At most 4096 interrupts. > 5. At most 1024 apertures. > > Todo: > 1. Encode the interrupt trigger information to exccode. > 2. Support complete CSR mclicbase when its number is fixed. > 3. Gave each aperture an independend address. > > It have passed my qtest case and freertos test. Welcome to have a try > for your hardware. > > Any advice is welcomed. Thanks very much. > > Zhiwei > > [1] specification website: https://github.com/riscv/riscv-fast-interrupt. > [2] Michael Clark origin work: > https://github.com/sifive/riscv-qemu/tree/sifive-clic. > > > LIU Zhiwei (11): > target/riscv: Add CLIC CSR mintstatus > target/riscv: Update CSR xintthresh in CLIC mode > hw/intc: Add CLIC device > target/riscv: Update CSR xie in CLIC mode > target/riscv: Update CSR xip in CLIC mode > target/riscv: Update CSR xtvec in CLIC mode > target/riscv: Update CSR xtvt in CLIC mode > target/riscv: Update CSR xnxti in CLIC mode > target/riscv: Update CSR mclicbase in CLIC mode > target/riscv: Update interrupt handling in CLIC mode > target/riscv: Update interrupt return in CLIC mode > > default-configs/devices/riscv32-softmmu.mak | 1 + > default-configs/devices/riscv64-softmmu.mak | 1 + > hw/intc/Kconfig | 3 + > hw/intc/meson.build | 1 + > hw/intc/riscv_clic.c | 836 ++++++++++++++++++++ > include/hw/intc/riscv_clic.h | 103 +++ > target/riscv/cpu.h | 9 + > target/riscv/cpu_bits.h | 32 + > target/riscv/cpu_helper.c | 117 ++- > target/riscv/csr.c | 247 +++++- > target/riscv/op_helper.c | 25 + > 11 files changed, 1363 insertions(+), 12 deletions(-) > create mode 100644 hw/intc/riscv_clic.c > create mode 100644 include/hw/intc/riscv_clic.h > > -- > 2.25.1 > > > After reviewing this patchset. I found that CLIC v0.8 spec is quite incomplete. It lacks all S-mode related CSRs. If you think that it's just the v0.8 spec issue for not covering all the required S-mode related CSRs -- and we should include them in CLIC v0.8 implementation even it's not documented explicitly. You can just ignore my comments in regard to S-mode CSRs for v0.8 CLIC. (Besides mintthresh, v0.8 spec does say that it holds the 8-bit field interrupt thresholds for each privilege mode.) Regards, Frank Chang --000000000000e5853905c5c1670d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C= =889=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:58=E5=AF=AB=E9=81=93= =EF=BC=9A
This patch set gives an implementation of "RISC-V= Core-Local Interrupt
Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where=
you can find the pdf format or the source code.

I take over the job from Michael Clark, who gave the first implementation of clic-v0.7 specification. If there is any copyright question, please
let me know.

Features:
1. support four kinds of trigger types.
2. Preserve the CSR WARL/WPRI semantics.
3. Option to select different modes, such as M/S/U or M/U.
4. At most 4096 interrupts.
5. At most 1024 apertures.

Todo:
1. Encode the interrupt trigger information to exccode.
2. Support complete CSR mclicbase when its number is fixed.
3. Gave each aperture an independend address.

It have passed my qtest case and freertos test. Welcome to have a try
for your hardware.

Any advice is welcomed. Thanks very much.

Zhiwei

[1] specification website: https://github.com/riscv/ris= cv-fast-interrupt.
[2] Michael Clark origin work: https://github.c= om/sifive/riscv-qemu/tree/sifive-clic.


LIU Zhiwei (11):
=C2=A0 target/riscv: Add CLIC CSR mintstatus
=C2=A0 target/riscv: Update CSR xintthresh in CLIC mode
=C2=A0 hw/intc: Add CLIC device
=C2=A0 target/riscv: Update CSR xie in CLIC mode
=C2=A0 target/riscv: Update CSR xip in CLIC mode
=C2=A0 target/riscv: Update CSR xtvec in CLIC mode
=C2=A0 target/riscv: Update CSR xtvt in CLIC mode
=C2=A0 target/riscv: Update CSR xnxti in CLIC mode
=C2=A0 target/riscv: Update CSR mclicbase in CLIC mode
=C2=A0 target/riscv: Update interrupt handling in CLIC mode
=C2=A0 target/riscv: Update interrupt return in CLIC mode

=C2=A0default-configs/devices/riscv32-softmmu.mak |=C2=A0 =C2=A01 +
=C2=A0default-configs/devices/riscv64-softmmu.mak |=C2=A0 =C2=A01 +
=C2=A0hw/intc/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A03 +
=C2=A0hw/intc/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
=C2=A0hw/intc/riscv_clic.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 836 ++++++++++++++++++++
=C2=A0include/hw/intc/riscv_clic.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 | 103 +++
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A09 +
=C2=A0target/riscv/cpu_bits.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 32 +
=C2=A0target/riscv/cpu_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0| 117 ++-
=C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 247 +++++-
=C2=A0target/riscv/op_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 25 +
=C2=A011 files changed, 1363 insertions(+), 12 deletions(-)
=C2=A0create mode 100644 hw/intc/riscv_clic.c
=C2=A0create mode 100644 include/hw/intc/riscv_clic.h

--
2.25.1



After reviewing this patchset.
I found that CLIC v0.8 spec is quite incomplete.
It lacks all = S-mode related CSRs.

If you think that it'= s just the v0.8 spec issue for not covering
all the required S-mo= de related CSRs -- and we should include them
in CLIC v0.8 implem= entation even it's not documented explicitly.
You can just ig= nore my comments in regard to S-mode CSRs for v0.8 CLIC.
(Besides= =C2=A0mintthresh, v0.8 spec does say that it holds the 8-bit field
interrupt thresholds for each privilege mode.)

R= egards,
Frank Chang
--000000000000e5853905c5c1670d--