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[209.85.214.177]) by smtp.gmail.com with ESMTPSA id c5sm10660801pfv.47.2021.06.27.05.08.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Jun 2021 05:08:40 -0700 (PDT) Received: by mail-pl1-f177.google.com with SMTP id c15so7261328pls.13; Sun, 27 Jun 2021 05:08:40 -0700 (PDT) X-Received: by 2002:a17:90a:9302:: with SMTP id p2mr21364671pjo.202.1624795720202; Sun, 27 Jun 2021 05:08:40 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-12-zhiwei_liu@c-sky.com> In-Reply-To: <20210409074857.166082-12-zhiwei_liu@c-sky.com> From: Frank Chang Date: Sun, 27 Jun 2021 20:08:29 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode To: LIU Zhiwei Content-Type: multipart/alternative; boundary="000000000000bc3d7d05c5be3b77" Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Alistair Francis , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000bc3d7d05c5be3b77 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:55=E5=AF=AB=E9=81=93=EF=BC=9A > When a vectored interrupt is selected and serviced, the hardware will > automatically clear the corresponding pending bit in edge-triggered mode. > This may lead to a lower priviledge interrupt pending forever. > > Therefore when interrupts return, pull a pending interrupt to service. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/op_helper.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 1eddcb94de..42563b22ba 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -24,6 +24,10 @@ > #include "exec/exec-all.h" > #include "exec/helper-proto.h" > > +#if !defined(CONFIG_USER_ONLY) > +#include "hw/intc/riscv_clic.h" > +#endif > + > /* Exceptions processing helpers */ > void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, > uint32_t exception, uintptr_t > pc) > @@ -130,6 +134,17 @@ target_ulong helper_sret(CPURISCVState *env, > target_ulong cpu_pc_deb) > mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); > mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); > env->mstatus =3D mstatus; > + > + if (riscv_clic_is_clic_mode(env)) { > + CPUState *cs =3D env_cpu(env); > + target_ulong spil =3D get_field(env->scause, SCAUSE_SPIL); > + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_SI= L, > spil); > + env->scause =3D set_field(env->scause, SCAUSE_SPIE, 0); > Should scause.spie set to 1? > + env->scause =3D set_field(env->scause, SCAUSE_SPP, PRV_U); > + qemu_mutex_lock_iothread(); > + riscv_clic_get_next_interrupt(env->clic, cs->cpu_index); > + qemu_mutex_unlock_iothread(); > + } > } > > riscv_cpu_set_mode(env, prev_priv); > @@ -172,6 +187,16 @@ target_ulong helper_mret(CPURISCVState *env, > target_ulong cpu_pc_deb) > riscv_cpu_set_virt_enabled(env, prev_virt); > } > > + if (riscv_clic_is_clic_mode(env)) { > + CPUState *cs =3D env_cpu(env); > + target_ulong mpil =3D get_field(env->mcause, MCAUSE_MPIL); > + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_MIL, > mpil); > + env->mcause =3D set_field(env->mcause, MCAUSE_MPIE, 0); > Should mcause.mpie set to 1? The xcause.xpp and xcause.xpie fields are modified following the behavior previously defined for xstatus.xpp and xstatus.xpie respectively. RISC-V Privilege spec: When executing an xRET instruction, xPIE is set to 1. Regards, Frank Chang > + env->mcause =3D set_field(env->mcause, MCAUSE_MPP, PRV_U); > + qemu_mutex_lock_iothread(); > + riscv_clic_get_next_interrupt(env->clic, cs->cpu_index); > + qemu_mutex_unlock_iothread(); > + } > return retpc; > } > > -- > 2.25.1 > > > --000000000000bc3d7d05c5be3b77 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C= =889=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:55=E5=AF=AB=E9=81=93= =EF=BC=9A
When a vectored interrupt is selected and serviced, th= e hardware will
automatically clear the corresponding pending bit in edge-triggered mode. This may lead to a lower priviledge interrupt pending forever.

Therefore when interrupts return, pull a pending interrupt to service.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
=C2=A0target/riscv/op_helper.c | 25 +++++++++++++++++++++++++
=C2=A01 file changed, 25 insertions(+)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 1eddcb94de..42563b22ba 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -24,6 +24,10 @@
=C2=A0#include "exec/exec-all.h"
=C2=A0#include "exec/helper-proto.h"

+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
=C2=A0/* Exceptions processing helpers */
=C2=A0void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0uint32_t exception, uintptr_t pc)
@@ -130,6 +134,17 @@ target_ulong helper_sret(CPURISCVState *env, target_ul= ong cpu_pc_deb)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mstatus =3D set_field(mstatus, MSTATUS_SP= IE, 1);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mstatus =3D set_field(mstatus, MSTATUS_SP= P, PRV_U);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->mstatus =3D mstatus;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (riscv_clic_is_clic_mode(env)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong spil =3D get_field(= env->scause, SCAUSE_SPIL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mintstatus =3D set_field= (env->mintstatus, MINTSTATUS_SIL, spil);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->scause =3D set_field(env= ->scause, SCAUSE_SPIE, 0);

Should sc= ause.spie set to 1?
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->scause =3D set_field(env= ->scause, SCAUSE_SPP, PRV_U);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_lock_iothread();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_clic_get_next_interrupt(en= v->clic, cs->cpu_index);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_unlock_iothread(); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0riscv_cpu_set_mode(env, prev_priv);
@@ -172,6 +187,16 @@ target_ulong helper_mret(CPURISCVState *env, target_ul= ong cpu_pc_deb)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0riscv_cpu_set_virt_enabled(env, prev_virt= );
=C2=A0 =C2=A0 =C2=A0}

+=C2=A0 =C2=A0 if (riscv_clic_is_clic_mode(env)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong mpil =3D get_field(env->mcause= , MCAUSE_MPIL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mintstatus =3D set_field(env->mints= tatus, MINTSTATUS_MIL, mpil);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mcause =3D set_field(env->mcause, M= CAUSE_MPIE, 0);

Should mcause.mpie set = to 1?
=C2=A0 The xcause.xpp and xcause.xpie fields are modified f= ollowing the behavior
=C2=A0 previously defined for xstatus.x= pp and xstatus.xpie respectively.

RISC-V Privi= lege spec:
=C2=A0 When executing an xRET instruction, xPIE is set= to 1.

Regards,
Frank Chang
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mcause =3D set_field(env->mcause, M= CAUSE_MPP, PRV_U);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_lock_iothread();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_clic_get_next_interrupt(env->clic, cs= ->cpu_index);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_unlock_iothread();
+=C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0return retpc;
=C2=A0}

--
2.25.1


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[209.85.214.177]) by smtp.gmail.com with ESMTPSA id c5sm10660801pfv.47.2021.06.27.05.08.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Jun 2021 05:08:40 -0700 (PDT) Received: by mail-pl1-f177.google.com with SMTP id c15so7261328pls.13; Sun, 27 Jun 2021 05:08:40 -0700 (PDT) X-Received: by 2002:a17:90a:9302:: with SMTP id p2mr21364671pjo.202.1624795720202; Sun, 27 Jun 2021 05:08:40 -0700 (PDT) MIME-Version: 1.0 References: <20210409074857.166082-1-zhiwei_liu@c-sky.com> <20210409074857.166082-12-zhiwei_liu@c-sky.com> In-Reply-To: <20210409074857.166082-12-zhiwei_liu@c-sky.com> From: Frank Chang Date: Sun, 27 Jun 2021 20:08:29 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode To: LIU Zhiwei Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , wxy194768@alibaba-inc.com Content-Type: multipart/alternative; boundary="000000000000bc3d7d05c5be3b77" Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 27 Jun 2021 12:08:44 -0000 --000000000000bc3d7d05c5be3b77 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable LIU Zhiwei =E6=96=BC 2021=E5=B9=B44=E6=9C=889=E6=97= =A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:55=E5=AF=AB=E9=81=93=EF=BC=9A > When a vectored interrupt is selected and serviced, the hardware will > automatically clear the corresponding pending bit in edge-triggered mode. > This may lead to a lower priviledge interrupt pending forever. > > Therefore when interrupts return, pull a pending interrupt to service. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/op_helper.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 1eddcb94de..42563b22ba 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -24,6 +24,10 @@ > #include "exec/exec-all.h" > #include "exec/helper-proto.h" > > +#if !defined(CONFIG_USER_ONLY) > +#include "hw/intc/riscv_clic.h" > +#endif > + > /* Exceptions processing helpers */ > void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, > uint32_t exception, uintptr_t > pc) > @@ -130,6 +134,17 @@ target_ulong helper_sret(CPURISCVState *env, > target_ulong cpu_pc_deb) > mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); > mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); > env->mstatus =3D mstatus; > + > + if (riscv_clic_is_clic_mode(env)) { > + CPUState *cs =3D env_cpu(env); > + target_ulong spil =3D get_field(env->scause, SCAUSE_SPIL); > + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_SI= L, > spil); > + env->scause =3D set_field(env->scause, SCAUSE_SPIE, 0); > Should scause.spie set to 1? > + env->scause =3D set_field(env->scause, SCAUSE_SPP, PRV_U); > + qemu_mutex_lock_iothread(); > + riscv_clic_get_next_interrupt(env->clic, cs->cpu_index); > + qemu_mutex_unlock_iothread(); > + } > } > > riscv_cpu_set_mode(env, prev_priv); > @@ -172,6 +187,16 @@ target_ulong helper_mret(CPURISCVState *env, > target_ulong cpu_pc_deb) > riscv_cpu_set_virt_enabled(env, prev_virt); > } > > + if (riscv_clic_is_clic_mode(env)) { > + CPUState *cs =3D env_cpu(env); > + target_ulong mpil =3D get_field(env->mcause, MCAUSE_MPIL); > + env->mintstatus =3D set_field(env->mintstatus, MINTSTATUS_MIL, > mpil); > + env->mcause =3D set_field(env->mcause, MCAUSE_MPIE, 0); > Should mcause.mpie set to 1? The xcause.xpp and xcause.xpie fields are modified following the behavior previously defined for xstatus.xpp and xstatus.xpie respectively. RISC-V Privilege spec: When executing an xRET instruction, xPIE is set to 1. Regards, Frank Chang > + env->mcause =3D set_field(env->mcause, MCAUSE_MPP, PRV_U); > + qemu_mutex_lock_iothread(); > + riscv_clic_get_next_interrupt(env->clic, cs->cpu_index); > + qemu_mutex_unlock_iothread(); > + } > return retpc; > } > > -- > 2.25.1 > > > --000000000000bc3d7d05c5be3b77 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
LIU Zhiwei <zhiwei_liu@c-sky.com> =E6=96=BC 2021=E5=B9=B44=E6=9C= =889=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=883:55=E5=AF=AB=E9=81=93= =EF=BC=9A
When a vectored interrupt is selected and serviced, th= e hardware will
automatically clear the corresponding pending bit in edge-triggered mode. This may lead to a lower priviledge interrupt pending forever.

Therefore when interrupts return, pull a pending interrupt to service.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
=C2=A0target/riscv/op_helper.c | 25 +++++++++++++++++++++++++
=C2=A01 file changed, 25 insertions(+)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 1eddcb94de..42563b22ba 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -24,6 +24,10 @@
=C2=A0#include "exec/exec-all.h"
=C2=A0#include "exec/helper-proto.h"

+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/riscv_clic.h"
+#endif
+
=C2=A0/* Exceptions processing helpers */
=C2=A0void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0uint32_t exception, uintptr_t pc)
@@ -130,6 +134,17 @@ target_ulong helper_sret(CPURISCVState *env, target_ul= ong cpu_pc_deb)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mstatus =3D set_field(mstatus, MSTATUS_SP= IE, 1);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mstatus =3D set_field(mstatus, MSTATUS_SP= P, PRV_U);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->mstatus =3D mstatus;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (riscv_clic_is_clic_mode(env)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong spil =3D get_field(= env->scause, SCAUSE_SPIL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mintstatus =3D set_field= (env->mintstatus, MINTSTATUS_SIL, spil);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->scause =3D set_field(env= ->scause, SCAUSE_SPIE, 0);

Should sc= ause.spie set to 1?
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->scause =3D set_field(env= ->scause, SCAUSE_SPP, PRV_U);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_lock_iothread();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_clic_get_next_interrupt(en= v->clic, cs->cpu_index);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_unlock_iothread(); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0riscv_cpu_set_mode(env, prev_priv);
@@ -172,6 +187,16 @@ target_ulong helper_mret(CPURISCVState *env, target_ul= ong cpu_pc_deb)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0riscv_cpu_set_virt_enabled(env, prev_virt= );
=C2=A0 =C2=A0 =C2=A0}

+=C2=A0 =C2=A0 if (riscv_clic_is_clic_mode(env)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong mpil =3D get_field(env->mcause= , MCAUSE_MPIL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mintstatus =3D set_field(env->mints= tatus, MINTSTATUS_MIL, mpil);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mcause =3D set_field(env->mcause, M= CAUSE_MPIE, 0);

Should mcause.mpie set = to 1?
=C2=A0 The xcause.xpp and xcause.xpie fields are modified f= ollowing the behavior
=C2=A0 previously defined for xstatus.x= pp and xstatus.xpie respectively.

RISC-V Privi= lege spec:
=C2=A0 When executing an xRET instruction, xPIE is set= to 1.

Regards,
Frank Chang
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->mcause =3D set_field(env->mcause, M= CAUSE_MPP, PRV_U);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_lock_iothread();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_clic_get_next_interrupt(env->clic, cs= ->cpu_index);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_mutex_unlock_iothread();
+=C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0return retpc;
=C2=A0}

--
2.25.1


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