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From: Emil Lenngren <emil.lenngren@gmail.com>
To: linux-pwm@vger.kernel.org
Subject: About disabling sun4i-pwm
Date: Wed, 14 Feb 2018 18:17:45 +0100	[thread overview]
Message-ID: <CAO1O6sebSwTR7ONQxq2WwPzMve5yq1z+EctrYgZ9Ynve-CU4AQ@mail.gmail.com> (raw)

Hi. I saw some discussions on disabling the PWM for sun4i and some
troubles about if it was being disabled during an active pulse, it
doesn't turn off the output but it stays active.

The original code is something like the following:
val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);

A suggested fix was to add a delay so it gets disabled during a low pulse.

But instead of the delay, I found it seems to be enough first writing
the ctrl reg with the PWM_EN bit disabled and then again writing the
ctrl reg with the PWM_CLK_GATING bit disabled, like this:

val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);

I have an Allwinner R8 chip, so not sure if that applies for the other
chips though. Anyone who has tested this more simpler fix?

/Emil

                 reply	other threads:[~2018-02-14 17:17 UTC|newest]

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