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From: Patrick Venture <venture@google.com>
Date: Wed, 11 Sep 2019 07:45:42 -0700
Message-ID: <CAO=notwLxLPEhxVj+A8Q0TcnSU2HVG_CFr5BvbwaSUU2bwgfjQ@mail.gmail.com>
Subject: Re: phosphor-ipmi-flash: Update over eSPI interface
To: Harry Sung1 <hsung1@lenovo.com>
Cc: Oskar Senft <osk@google.com>, Andrew MS1 Peng <pengms1@lenovo.com>, 
 "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>
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On Wed, Sep 11, 2019 at 1:59 AM Harry Sung1 <hsung1@lenovo.com> wrote:
>
>
> > On Mon, Sep 9, 2019 at 7:01 AM Oskar Senft <osk@google.com> wrote:
> > >
> > > Hi Harry
> > >
> > > What's the behavior on eSPI? I assume you still have the aspeed-lpc-c=
trl
> > enabled, right?
> > >
> > > Thanks
> > > Oskar.
>
> Hi Oskar,
> Yes, I still enabled the aspeed-lpc-ctrl in my build. Because phosphor-ip=
mi-flash has some mandatory actions on /dev/aspeed-lpc-ctrl before flash (s=
ettings for HICR5, HICR7 and HICR8) even though these settings are meaningl=
ess for eSPI.
>
> Currently, I set ESPI084 (source address) and ESPI088 (target address) re=
gisters manually because linux seems not have a driver can help us to set E=
SPI084 and ESPI088.
>
> Due to the limitation of AST2500, we can only write 256 bytes in one writ=
e operation (write shared memory).
> Based on the test result, it takes about 30 mins to transfer a 32MB image=
 over eSPI.

:( wow, that's unfortunately rather slow.

>
> Thanks,
> Harry
> > >
> > > On Mon, Sep 9, 2019 at 4:41 AM Harry Sung1 <hsung1@lenovo.com> wrote:
> > >>
> > >> Hi Patrick,
> > >>
> > >>
> > >>
> > >> I found =E2=80=9Cphosphor-ipmi-flash=E2=80=9D have not support flash=
 over eSPI yet.
> > >>
> > >> May I ask if you have any plans to support flash over eSPI?
> > >>
> > >>
> > >>
> > >> I have done a simple test about shared memory between host and BMC :
> > >>
> > >> The shared memory is work after I set ESPI084 (source address) and E=
SPI088
> > (target address) registers.
> > >>
> > >> But it has an limitation that only 256 bytes are available on each p=
age (4KB).
> > >>
> > >>
> > >> For example, if host address starts to write from 0xFE0B0000 (BMC
> > >> reserved enough memory already)
> > >>
> > >> Writable area are:
> > >>
> > >> 0xFE0B0000 ~ 0xFE0B00FF
> > >>
> > >> 0xFE0B1000 ~ 0xFE0B10FF
> > >>
> > >> 0xFE0B2000 ~ 0xFE0B20FF
> > >>
> > >> 0xFE0B3000 ~ 0xFE0B30FF
> > >>
> > >> =E2=80=A6
> > >>
> > >> =E2=80=A6
> > >>
> > >> =E2=80=A6
> > >>
> > >>
> > >>
> > >>
> > >>
> > >> Thanks,
> > >> Harry
> >
> > Harry, currently there's no plan to implement it as I have no method of=
 testing
> > it,  However, it should prove fairly straightforward to add another opt=
ion to
> > the transport mechanism list.  Please let me know if you run into any
> > blockers.
>
> Hi Patrick,
> Got it. The better way to set eSPI register is setting them by the driver=
, right?
> For quick validation, I am going to use the " ipmilpc" interface and set =
necessary eSPI registers manually.

I don't know as much about the eSPI variation of this.  ipmilpc uses
whatever LPC memory shared option is available (in coordination with
the host+bmc).  If eSPI doesn't use the aspeed-lpc-ctrl driver for
what it needs, then perhaps a new option should be added ipmiespi?

>
> Thanks,
> Harry