From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754588AbdC2IJU (ORCPT ); Wed, 29 Mar 2017 04:09:20 -0400 Received: from mail-pg0-f54.google.com ([74.125.83.54]:34760 "EHLO mail-pg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753932AbdC2IHy (ORCPT ); Wed, 29 Mar 2017 04:07:54 -0400 MIME-Version: 1.0 In-Reply-To: References: <1489417599-31308-1-git-send-email-cedric.madianga@gmail.com> <1489417599-31308-2-git-send-email-cedric.madianga@gmail.com> <20170320215250.wwhq6lzwe45jmwks@rob-hp-laptop> From: "M'boumba Cedric Madianga" Date: Wed, 29 Mar 2017 10:07:51 +0200 Message-ID: Subject: Re: [PATCH 1/2] dt-bindings: Document the STM32 MDMA bindings To: Rob Herring Cc: Vinod Koul , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Dan Williams , dmaengine@vger.kernel.org, "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, > stm32 is not a specific SoC. Compatible strings should be specific to > an SoC (with fallback strings to whatever they are compatible with) so > you can handle SoC specific differences or errata. Ok I see. I will add a more specific SoC description in my compatible. Thanks. > I still don't understand. Is the difference in DMA addresses vs. CPU > addresses? If so, you should dma-ranges to translate these. Not really. In fact, the MDMA controller provides a master AXI interface for memories like DDR/SRAM and peripheral registers access (system access port). It also provides a master AHB interface only for Cortex-M7 TCM memory access (TCM access port). So the goal of this st,ahb-addr-masks property is to list all TCM addresses avalaible in the SoC, in order to correctly configure the MDMA as an AHB master in that particular case. For all other cases (other memories or peripheral registers access), the MDMA will act as AXI master. Hope it helps to understand. BR, Cedric From mboxrd@z Thu Jan 1 00:00:00 1970 From: "M'boumba Cedric Madianga" Subject: Re: [PATCH 1/2] dt-bindings: Document the STM32 MDMA bindings Date: Wed, 29 Mar 2017 10:07:51 +0200 Message-ID: References: <1489417599-31308-1-git-send-email-cedric.madianga@gmail.com> <1489417599-31308-2-git-send-email-cedric.madianga@gmail.com> <20170320215250.wwhq6lzwe45jmwks@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Rob Herring Cc: Mark Rutland , "devicetree@vger.kernel.org" , Alexandre Torgue , Vinod Koul , "linux-kernel@vger.kernel.org" , Maxime Coquelin , dmaengine@vger.kernel.org, Dan Williams , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org Hi Rob, > stm32 is not a specific SoC. Compatible strings should be specific to > an SoC (with fallback strings to whatever they are compatible with) so > you can handle SoC specific differences or errata. Ok I see. I will add a more specific SoC description in my compatible. Thanks. > I still don't understand. Is the difference in DMA addresses vs. CPU > addresses? If so, you should dma-ranges to translate these. Not really. In fact, the MDMA controller provides a master AXI interface for memories like DDR/SRAM and peripheral registers access (system access port). It also provides a master AHB interface only for Cortex-M7 TCM memory access (TCM access port). So the goal of this st,ahb-addr-masks property is to list all TCM addresses avalaible in the SoC, in order to correctly configure the MDMA as an AHB master in that particular case. For all other cases (other memories or peripheral registers access), the MDMA will act as AXI master. Hope it helps to understand. BR, Cedric From mboxrd@z Thu Jan 1 00:00:00 1970 From: cedric.madianga@gmail.com (M'boumba Cedric Madianga) Date: Wed, 29 Mar 2017 10:07:51 +0200 Subject: [PATCH 1/2] dt-bindings: Document the STM32 MDMA bindings In-Reply-To: References: <1489417599-31308-1-git-send-email-cedric.madianga@gmail.com> <1489417599-31308-2-git-send-email-cedric.madianga@gmail.com> <20170320215250.wwhq6lzwe45jmwks@rob-hp-laptop> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Rob, > stm32 is not a specific SoC. Compatible strings should be specific to > an SoC (with fallback strings to whatever they are compatible with) so > you can handle SoC specific differences or errata. Ok I see. I will add a more specific SoC description in my compatible. Thanks. > I still don't understand. Is the difference in DMA addresses vs. CPU > addresses? If so, you should dma-ranges to translate these. Not really. In fact, the MDMA controller provides a master AXI interface for memories like DDR/SRAM and peripheral registers access (system access port). It also provides a master AHB interface only for Cortex-M7 TCM memory access (TCM access port). So the goal of this st,ahb-addr-masks property is to list all TCM addresses avalaible in the SoC, in order to correctly configure the MDMA as an AHB master in that particular case. For all other cases (other memories or peripheral registers access), the MDMA will act as AXI master. Hope it helps to understand. BR, Cedric