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AO0yUKUorbGVx4UzFE0TZPPvyML4cj2hPA10Yi/sZBaLfjA8jQJRy2yA DxAexPqhNCbBn+0RiD6huFx8dG8v02Y3DAuSq5E= X-Google-Smtp-Source: AK7set/6YC+GV8KkMJqP+ka5+QupP/MWUbeOO5D2SV4WVG2hW/D+MkzZrAZ3nYvrM/EUq5F2FmGMK4716RLSABYHRIE= X-Received: by 2002:a05:6808:1a1d:b0:383:fef9:6cac with SMTP id bk29-20020a0568081a1d00b00383fef96cacmr948825oib.9.1679488693956; Wed, 22 Mar 2023 05:38:13 -0700 (PDT) MIME-Version: 1.0 References: <20230305114634.h6wyi26ohuzuamfg@pali> <20230305160416.xc7wlzmkaociwcf7@pali> <20230306115325.5pfb4lheobjg2tsi@pali> <20230319162242.eq5rsxofrrq2ukdg@pali> <20230320173350.j4o7tunn7ijpbhyr@pali> <20230321080758.5cmlygv63idaecth@pali> In-Reply-To: <20230321080758.5cmlygv63idaecth@pali> From: Martin Rowe Date: Wed, 22 Mar 2023 12:38:02 +0000 Message-ID: Subject: Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot To: =?UTF-8?Q?Pali_Roh=C3=A1r?= Cc: u-boot@lists.denx.de Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.39 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Tue, 21 Mar 2023 at 08:08, Pali Roh=C3=A1r wrote: > On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > > On Mon, 20 Mar 2023 at 17:33, Pali Roh=C3=A1r wrote: > > > > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > > > On Sun, 19 Mar 2023 at 16:22, Pali Roh=C3=A1r wro= te: > > > > > > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Roh=C3=A1r = wrote: > > > > > > > > > > > > > Could you try to print mmc->part_config (ideally as early as > > > possible)? > > > > > > > > > > > > > > > > > > > In SPL mmc->part_config is 255 > > > > > > In main u-boot at the start of clearfog.c board_init() > > > mmc->part_config > > > > > is > > > > > > 255 > > > > > > In main u-boot at the start of clearfog.c checkboard() > > > mmc->part_config > > > > > is > > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > > > > > > > > 255 is uninitialized value. > > > > > > > > > > > If I set partition_enable to 2, I get the same result except th= e > > > value is > > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for t= he > > > last > > > > > value > > > > > > > > > > Try to change "access" bits. > > > > > > > > > > > > > > > > > BootROM - 1.73 > > > > > > > > > > > > Booting from MMC > > > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > 10:05:32 > > > > > > +1000) > > > > > > High speed PHY - Version: 2.0 > > > > > > EEPROM TLV detection failed: Using static config for Clearfog > Pro. > > > > > > Detected Device ID 6828 > > > > > > board SerDes lanes topology details: > > > > > > | Lane # | Speed | Type | > > > > > > -------------------------------- > > > > > > | 0 | 3 | SATA0 | > > > > > > | 1 | 0 | SGMII1 | > > > > > > | 2 | 5 | PCIe1 | > > > > > > | 3 | 5 | USB3 HOST1 | > > > > > > | 4 | 5 | PCIe2 | > > > > > > | 5 | 0 | SGMII2 | > > > > > > -------------------------------- > > > > > > High speed PHY - Ended Successfully > > > > > > mv_ddr: 14.0.0 > > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Wind= ow > > > > > > mv_ddr: completed successfully > > > > > > spl.c spl_boot_device part_config =3D 255 > > > > > > Trying to boot from MMC1 > > > > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > 10:05:32 > > > +1000) > > > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > > clearfog.c board_init part_config =3D 255 > > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > > MMC: mv_sdh: 0 > > > > > > Loading Environment from MMC... *** Warning - bad CRC, using > default > > > > > > environment > > > > > > > > > > > > Model: SolidRun Clearfog A1 > > > > > > clearfog.c checkboard part_config =3D 8 > > > > > > Board: SolidRun Clearfog Pro > > > > > > Net: > > > > > > Warning: ethernet@70000 (eth1) using random MAC address - > > > > > 32:16:0e:b4:d1:d8 > > > > > > eth1: ethernet@70000 > > > > > > Warning: ethernet@30000 (eth2) using random MAC address - > > > > > 72:30:3f:79:07:12 > > > > > > , eth2: ethernet@30000 > > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > > > 82:fb:71:23:46:4f > > > > > > , eth3: ethernet@34000 > > > > > > Hit any key to stop autoboot: 0 > > > > > > =3D> mmc partconf 0 > > > > > > EXT_CSD[179], PARTITION_CONFIG: > > > > > > BOOT_ACK: 0x0 > > > > > > BOOT_PARTITION_ENABLE: 0x1 > > > > > > PARTITION_ACCESS: 0x0 > > > > > > > > > > > > > > > > > > > > > > > > BootROM - 1.73 > > > > > > > > > > > > Booting from MMC > > > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > 10:05:32 > > > > > > +1000) > > > > > > High speed PHY - Version: 2.0 > > > > > > EEPROM TLV detection failed: Using static config for Clearfog > Pro. > > > > > > Detected Device ID 6828 > > > > > > board SerDes lanes topology details: > > > > > > | Lane # | Speed | Type | > > > > > > -------------------------------- > > > > > > | 0 | 3 | SATA0 | > > > > > > | 1 | 0 | SGMII1 | > > > > > > | 2 | 5 | PCIe1 | > > > > > > | 3 | 5 | USB3 HOST1 | > > > > > > | 4 | 5 | PCIe2 | > > > > > > | 5 | 0 | SGMII2 | > > > > > > -------------------------------- > > > > > > High speed PHY - Ended Successfully > > > > > > mv_ddr: 14.0.0 > > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Wind= ow > > > > > > mv_ddr: completed successfully > > > > > > spl.c spl_boot_device part_config =3D 255 > > > > > > Trying to boot from MMC1 > > > > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > 10:05:32 > > > +1000) > > > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > > clearfog.c board_init part_config =3D 255 > > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > > MMC: mv_sdh: 0 > > > > > > Loading Environment from MMC... *** Warning - bad CRC, using > default > > > > > > environment > > > > > > > > > > > > Model: SolidRun Clearfog A1 > > > > > > clearfog.c checkboard part_config =3D 16 > > > > > > Board: SolidRun Clearfog Pro > > > > > > Net: > > > > > > Warning: ethernet@70000 (eth1) using random MAC address - > > > > > 92:5a:fc:14:e8:f6 > > > > > > eth1: ethernet@70000 > > > > > > Warning: ethernet@30000 (eth2) using random MAC address - > > > > > 42:9c:d8:3a:cb:b2 > > > > > > , eth2: ethernet@30000 > > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > > > c6:99:20:f4:02:a0 > > > > > > , eth3: ethernet@34000 > > > > > > Hit any key to stop autoboot: 0 > > > > > > =3D> mmc partconf 0 > > > > > > EXT_CSD[179], PARTITION_CONFIG: > > > > > > BOOT_ACK: 0x0 > > > > > > BOOT_PARTITION_ENABLE: 0x2 > > > > > > PARTITION_ACCESS: 0x0 > > > > > > > > > > > > > > > > Are both logs from the configuration when SPL+u-boot is stored on > > > Boot0? > > > > > Could you try to erase Boot0 and store SPL+u-boot to Boot1? I'm > > > > > interested to see if "access" bits are changed in SPL (before > loading > > > > > main u-boot). > > > > > > > > > > > I'm having trouble trying to find the hooks which run between > > > board_init > > > > > > and checkboard. If you can point me in the right direction I'm > happy > > > to > > > > > > re-run and try to narrow down where the valid values are being > set > > > from. > > > > > > > > > > Print it directly in drivers/mmc/mmc.c mmc_startup_v4() where > > > > > mmc->part_config =3D is set from ext_csd[EXT_CSD_PART_CONF] regis= ter. > > > > > I want to see original value from EXT_CSD_PART_CONF. > > > > > > > > > > I do not know which hook is the best, so printing it from mmc.c > driver > > > > > should work better. > > > > > > > > > > > > > u-boot in boot0, partconf set to 0x1: > > > > mmc->part_config =3D 8 > > > > > > > > u-boot in boot0, partconf set to 0x2: > > > > mmc->part_config =3D 16 > > > > > > > > u-boot in boot1 (boot0 zeroed), partconf set to 0x1: > > > > mmc->part_config =3D 8 > > > > > > > > u-boot in boot1 (boot0 zeroed), partconf set to 0x2: > > > > mmc->part_config =3D 16 > > > > > > Ah, that does not look useful :-( > > > > > > Just to confirm, is this output from SPL or from main U-Boot? > > > > > > > Definitely SPL. I triple checked because I was also disappointed with > those > > results. With BootROM hardcoded with its boot order it seems like neith= er > > CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION nor relying on > > mmc->part_config is going to work well. > > In emmc spec is written: > > Each time the host wants to access a partition the following flow shall b= e > executed: > 1. Set PARTITION_ACCESS bits in the PARTITION_CONFIG field of the Extende= d > CSD register in order to address one of the partitions > 2. Issue commands referred to the selected partition > 3. Restore default access to the User Data Area or re-direction the acces= s > to another partition > All the reset events (CMD0 or hardware reset) will restore the access by > default to the User Data Area. > > I'm feeling that partition_access bits should be preserved between > reading data from boot0 and starting SPL. And these bits somehow could > be used to determinate from which source bootrom loaded SPL. Maybe the > last point ("all the reset events...") applies there and u-boot mmc > driver does some reset in its init phase? And need to figure > out how to read PARTITION_ACCESS without u-boot's mmc driver? > I enabled MMC tracing and added some printfs in mmc.c functions to see if we can get a better idea of where best to read the value from: BootROM - 1.73 Booting from MMC U-Boot SPL 2023.04-rc4-00342-g7e562609bb-dirty (Mar 22 2023 - 22:14:28 +1000) High speed PHY - Version: 2.0 EEPROM TLV detection failed: Using static config for Clearfog Pro. Detected Device ID 6828 board SerDes lanes topology details: | Lane # | Speed | Type | -------------------------------- | 0 | 3 | SATA0 | | 1 | 0 | SGMII1 | | 2 | 5 | PCIe1 | | 3 | 5 | USB3 HOST1 | | 4 | 5 | PCIe2 | | 5 | 0 | SGMII2 | -------------------------------- High speed PHY - Ended Successfully mv_ddr: 14.0.0 DDR3 Training Sequence - Switching XBAR Window to FastPath Window mv_ddr: completed successfully Trying to boot from MMC1 =3D=3D=3Dmmc_start_init start=3D=3D=3D =3D=3D=3DGetting ext_csd=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 =3D=3D=3Dmmc_power_on=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 =3D=3D=3Dmmc_select_mode=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 =3D=3D=3Dmmc_mode2freq=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 =3D=3D=3Dmmc_set_initial_state=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:8 ARG 0x000001aa RET -110 CMD_SEND:55 ARG 0x00000000 RET -110 CMD_SEND:0 ARG 0x00000000 MMC_RSP_NONE CMD_SEND:1 ARG 0x00000000 MMC_RSP_R3,4 0x40ff8080 CMD_SEND:1 ARG 0x40300080 MMC_RSP_R3,4 0x40ff8080 CMD_SEND:1 ARG 0x40300080 MMC_RSP_R3,4 0xc0ff8080 =3D=3D=3Dmmc_start_init end=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 CMD_SEND:2 ARG 0x00000000 MMC_RSP_R2 0x15010038 0x474d4534 0x52010418 0xfc4f7300 DUMPING DATA 000 - 15 01 00 38 004 - 47 4d 45 34 008 - 52 01 04 18 012 - fc 4f 73 00 CMD_SEND:3 ARG 0x00010000 MMC_RSP_R1,5,6,7 0x00000500 CMD_SEND:9 ARG 0x00010000 MMC_RSP_R2 0xd0270132 0x0f5903ff 0xf6dbffef 0x8e404000 DUMPING DATA 000 - d0 27 01 32 004 - 0f 59 03 ff 008 - f6 db ff ef 012 - 8e 40 40 00 =3D=3D=3Dmmc_select_mode=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 =3D=3D=3Dmmc_mode2freq=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 0 CMD_SEND:7 ARG 0x00010000 MMC_RSP_R1,5,6,7 0x00000700 CMD_SEND:8 ARG 0x00000000 MMC_RSP_R1,5,6,7 0x00000900 =3D=3D=3Dmmc_startup_v4=3D=3D=3D =3D=3D=3Dmmc->ext_csd[EXT_CSD_PART_CONF] =3D 8