From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,LOTS_OF_MONEY,MAILING_LIST_MULTI,MONEY_NOHTML, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FA79C07E96 for ; Thu, 8 Jul 2021 20:59:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 41ED261420 for ; Thu, 8 Jul 2021 20:59:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230442AbhGHVCX (ORCPT ); Thu, 8 Jul 2021 17:02:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230425AbhGHVCX (ORCPT ); Thu, 8 Jul 2021 17:02:23 -0400 Received: from mail-il1-x12f.google.com (mail-il1-x12f.google.com [IPv6:2607:f8b0:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17483C061574 for ; Thu, 8 Jul 2021 13:59:40 -0700 (PDT) Received: by mail-il1-x12f.google.com with SMTP id h3so7970470ilc.9 for ; Thu, 08 Jul 2021 13:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=u0nJ5EypAihw/HUezUvxgsNKaLjT3N+h+V7waposDmE=; b=BFRavtR25uNMSAMxy1BrcpGAB6djxvxR1hryroHuucP5XxFeh/zHISP0RskNbjeFBs wnZLi4J33dxeEv+wla/xQi+afchuzSaq+OxnTm2KDrgXAD/qoTQIEt2w+gstQLWd9hKy /I3BN12z3wgGxp6wYOPOy+d2qL2HovXM+VxAyPZ59BeXjjP8uEt1U6LEzqLV+r+vdquM KE7fMicgGE2pyL8AeSD3/eYDE7PF2W9E6l+YrD4koousLqRaGHypdom2akKVPY7pDO6R 4Ox69m84V7XwsxkVtcRr6Vy4xZl6nwSYUDMI2gX3w4Hmd2bcublkHHEp280qvguRHknp yUDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=u0nJ5EypAihw/HUezUvxgsNKaLjT3N+h+V7waposDmE=; b=bgyHUlWdxp7ZMNCBurx95qWFp1+BbF4A776TQgdjsoUFwsfSTg3f5Kr5mWZkEBnBYY FNt8SdvD3GRi1DJQn5F1qrTzmi8V9dY03vJnA4z0k5wA3fXwjUtJ9ZBV8BcKTMdf47ih e6velwAsc3CJunTh1J1LoJdjUA5bJ/7gmbZ8lQfJSAifUO7Hbu8NBfl01PKJbGNUta+y LngLLI6DZjG2TADhqAs6nD7TqIbWrbZG7feY44doZeKnLYPU5+g2hjY6Is9oZuCTceRE WdIJHJozKPFGSVem81dJb6TLK/fBHo6nYaAmgUdm1Gz9YFNuJKXT3XnkxHu3TsXmn5Qt FbtA== X-Gm-Message-State: AOAM530sJ3xppZTTSpxZnrctf2xRDMFfmKNBzn99ehCTTJsYf5w4gvSe VfXUuLBj0yryjkVtqtO3g/fySkefGdjf6m4rNxE= X-Google-Smtp-Source: ABdhPJzy6vsjNz305EeGV0LnSoMUm2tEd1A0t7cwc55gUpsOibEaNF5OzUOv4C+VlyLgm30G01ryHcmlTl1caL2VYSI= X-Received: by 2002:a92:d08b:: with SMTP id h11mr8138938ilh.32.1625777979532; Thu, 08 Jul 2021 13:59:39 -0700 (PDT) MIME-Version: 1.0 References: <20210527124356.22367-1-will@kernel.org> <59800d6c-364a-f4be-e341-c5b531657ba3@arm.com> <20210706133314.GB20327@willie-the-truck> <87zguz7b6b.wl-maz@kernel.org> In-Reply-To: From: Jeffrey Hugo Date: Thu, 8 Jul 2021 14:59:28 -0600 Message-ID: Subject: Re: [PATCH] arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) To: Arnd Bergmann Cc: Yassine Oudjana , Marc Zyngier , Will Deacon , Robin Murphy , Catalin Marinas , Ard Biesheuvel , Android Kernel Team , Linux ARM , Mark Rutland , Vincent Whitchurch , linux-arm-msm , Bjorn Andersson Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Jul 7, 2021 at 8:41 AM Jeffrey Hugo wrote: > > On Wed, Jul 7, 2021 at 3:30 AM Arnd Bergmann wrote: > > > > On Tue, Jul 6, 2021 at 6:20 PM Will Deacon wrote: > > > > > > I think the million dollar question is whether the 128-byte cache-lines > > > live in a cache above the PoC or not. If it's just a system level cache > > > through which all DMA is "coherent", then it doesn't matter. > > > > On Wed, Jul 7, 2021 at 10:24 AM Yassine Oudjana > > wrote: > > > > > > On Wednesday, July 7th, 2021 at 12:33 AM, Arnd Bergmann wrote: > > > > On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana y.oudjana@protonmail.com wrote: > > > > > > > > > > $ numactl -C 0 line -M 1M > > > > > 128 > > > > > $ numactl -C 3 line -M 1M > > > > > 128 > > > > > > > > Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64 > > > > byte L1 line size that the 'cache' test reported? > > > > > > $ numactl -C 0 line -M 128K > > > 64 > > > $ numactl -C 3 line -M 128K > > > 64 > > > > Ok, so this seems to confirm that the L1 uses 64 byte lines, while the L2 (or > > possibly L3) uses 128 byte lines. > > > > On Wed, Jul 7, 2021 at 12:27 AM Bjorn Andersson > > wrote: > > > > > > I can confirm that MSM8996, and a few derivatives, has 128 byte cache lines. > > > > Ok, thanks. Assuming this is an outer cache and the L1 indeed has a smaller line > > size, can you also confirm that this 128 byte lines are north of the point of > > coherency? > > Finding this old documentation has been painful :) > > L0 I 64 byte cacheline > L1 I 64 > L1 D 64 > L2 unified 128 (shared between the CPUs of a duplex) > > I believe L2 is within the POC, but I'm trying to dig up the old > documentation to confirm. Was able to track down a friendly hardware designer. The POC lies between L2 and L3. Hope this helps. > > In other words, does the CTR_EL0.DminLine field also show 128 bytes > > (in which case > > it seems we already lost)? And if not, does a CPU store to the second half of a > > 128 byte L2 line cause DMA data in the first half to be clobbered? > > Per the documentation I'm seeing, CTR_EL0.DminLine should show 128 > bytes. I don't have hardware handy to confirm. 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 7, 2021 at 8:41 AM Jeffrey Hugo wrote: > > On Wed, Jul 7, 2021 at 3:30 AM Arnd Bergmann wrote: > > > > On Tue, Jul 6, 2021 at 6:20 PM Will Deacon wrote: > > > > > > I think the million dollar question is whether the 128-byte cache-lines > > > live in a cache above the PoC or not. If it's just a system level cache > > > through which all DMA is "coherent", then it doesn't matter. > > > > On Wed, Jul 7, 2021 at 10:24 AM Yassine Oudjana > > wrote: > > > > > > On Wednesday, July 7th, 2021 at 12:33 AM, Arnd Bergmann wrote: > > > > On Tue, Jul 6, 2021 at 7:15 PM Yassine Oudjana y.oudjana@protonmail.com wrote: > > > > > > > > > > $ numactl -C 0 line -M 1M > > > > > 128 > > > > > $ numactl -C 3 line -M 1M > > > > > 128 > > > > > > > > Can you rerun the the 'line' test with '-M 128K' to see if that confirms the 64 > > > > byte L1 line size that the 'cache' test reported? > > > > > > $ numactl -C 0 line -M 128K > > > 64 > > > $ numactl -C 3 line -M 128K > > > 64 > > > > Ok, so this seems to confirm that the L1 uses 64 byte lines, while the L2 (or > > possibly L3) uses 128 byte lines. > > > > On Wed, Jul 7, 2021 at 12:27 AM Bjorn Andersson > > wrote: > > > > > > I can confirm that MSM8996, and a few derivatives, has 128 byte cache lines. > > > > Ok, thanks. Assuming this is an outer cache and the L1 indeed has a smaller line > > size, can you also confirm that this 128 byte lines are north of the point of > > coherency? > > Finding this old documentation has been painful :) > > L0 I 64 byte cacheline > L1 I 64 > L1 D 64 > L2 unified 128 (shared between the CPUs of a duplex) > > I believe L2 is within the POC, but I'm trying to dig up the old > documentation to confirm. Was able to track down a friendly hardware designer. The POC lies between L2 and L3. Hope this helps. > > In other words, does the CTR_EL0.DminLine field also show 128 bytes > > (in which case > > it seems we already lost)? And if not, does a CPU store to the second half of a > > 128 byte L2 line cause DMA data in the first half to be clobbered? > > Per the documentation I'm seeing, CTR_EL0.DminLine should show 128 > bytes. I don't have hardware handy to confirm. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel