From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabio Estevam Subject: Re: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28 Date: Fri, 3 Aug 2012 10:46:06 -0300 Message-ID: References: <1343076052-27312-1-git-send-email-marex@denx.de> <1343076052-27312-7-git-send-email-marex@denx.de> <20120803153815.758dc064@skate> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: Marek Vasut , Fabio Estevam , Shawn Guo , Mark Brown , Attila Kinali , spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, Chris Ball , Dong Aisheng , Linux ARM kernel To: Thomas Petazzoni Return-path: In-Reply-To: <20120803153815.758dc064@skate> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Id: linux-spi.vger.kernel.org On Fri, Aug 3, 2012 at 10:38 AM, Thomas Petazzoni wrote: > > It sounds really strange to manipulate WAIT_FOR_CMD and WAIT_FOR_IRQ > bits to adjust the chip select, and when reading the driver, it seemed > suspicious to me. After going through the datasheet, indeed those bits > are the appropriate one to select between the SS0, SS1 and SS2 chip > selects, but I find the code not really obvious. Would it be possible > to make it more obvious either by adding or comment or doing something > like: > > /* Should be put in some header file */ > #define BM_SSP_CTRL0_SPI_CS_BITS (20) > > +static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs) > +{ > + struct mxs_ssp *ssp = &spi->ssp; > + > + writel(0x3 << BM_SSP_CTRL0_SPI_CS_BITS, > + ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); > + writel(cs, > + ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); > +} I agree with Thomas. In U-boot I did the following in order to be able to select the different chip selects: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=148ca64f327a89ef77e84756f5d351af33e59b64 Thanks, Fabio Estevam ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ From mboxrd@z Thu Jan 1 00:00:00 1970 From: festevam@gmail.com (Fabio Estevam) Date: Fri, 3 Aug 2012 10:46:06 -0300 Subject: [PATCH 06/10 V2] spi: Add SPI driver for mx233/mx28 In-Reply-To: <20120803153815.758dc064@skate> References: <1343076052-27312-1-git-send-email-marex@denx.de> <1343076052-27312-7-git-send-email-marex@denx.de> <20120803153815.758dc064@skate> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Aug 3, 2012 at 10:38 AM, Thomas Petazzoni wrote: > > It sounds really strange to manipulate WAIT_FOR_CMD and WAIT_FOR_IRQ > bits to adjust the chip select, and when reading the driver, it seemed > suspicious to me. After going through the datasheet, indeed those bits > are the appropriate one to select between the SS0, SS1 and SS2 chip > selects, but I find the code not really obvious. Would it be possible > to make it more obvious either by adding or comment or doing something > like: > > /* Should be put in some header file */ > #define BM_SSP_CTRL0_SPI_CS_BITS (20) > > +static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs) > +{ > + struct mxs_ssp *ssp = &spi->ssp; > + > + writel(0x3 << BM_SSP_CTRL0_SPI_CS_BITS, > + ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); > + writel(cs, > + ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); > +} I agree with Thomas. In U-boot I did the following in order to be able to select the different chip selects: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=148ca64f327a89ef77e84756f5d351af33e59b64 Thanks, Fabio Estevam