From mboxrd@z Thu Jan  1 00:00:00 1970
From: Fabio Estevam <festevam@gmail.com>
Date: Wed, 15 Jun 2016 07:45:33 -0300
Subject: [U-Boot] [PATCH V2 2/3] fsl_esdhc: Update clock enable bits for
	USDHC
In-Reply-To: <1465959182-13561-2-git-send-email-van.freenix@gmail.com>
References: <1465959182-13561-1-git-send-email-van.freenix@gmail.com>
 <1465959182-13561-2-git-send-email-van.freenix@gmail.com>
Message-ID: <CAOMZO5AkZp6iFW4ZneD790N527JAFaU=P-0iRJyFO6+otScQSw@mail.gmail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

On Tue, Jun 14, 2016 at 11:53 PM, Peng Fan <van.freenix@gmail.com> wrote:
> From: Ye Li <ye.li@nxp.com>
>
> The USDHC move the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
> HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
> register. The driver uses RSTA to replace the clock gate off
> operation. But this is not a good solution. This is because:
> 1. when using RSTA, we should wait this bit to clear by itself. This is not
>    implemeneted in the code.
> 2. After RSTA is set, it is recommended that the Host Driver reset the
>    external card and reinitialize it.
>
> So in this patch, we change to use the vendorspec registers for these bits
> operation.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <van.freenix@gmail.com>
> Cc: York Sun <york.sun@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>

Tested-by: Fabio Estevam <fabio.estevam@nxp.com>